AK7750 Datasheet, PDF (49/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
(7) Microprocessor Interface
The microprocessor interface uses 6 control signals, RQ ( ReQuest Bar ), SCLK ( Serial data input
Clock ), SI ( Serial data Input ), SO ( Serial data Output ), RDY ( ReaDY ), DRDY ( Data ReaDY ).
The AK7750 has 2 types of write and read operations – write / read during reset (usually refers to system
reset) and, write / read during normal operation.
During reset, it is possible to write data into the control registers, program RAM, coefficient RAM, offset
RAM and to write external conditional jump codes. It is possible to read data from the control registers,
program RAM, coefficient RAM and offset RAM.
During normal operation, it is possible to write data into coefficient RAM, offset RAM, and to write external
conditional jump codes. It is also possible to read data on the DBUS ( Data Bus ) via SO and to read data
from control registers. Data is input or output in serial form with MSB first.
The interface between the microprocessor and the AK7750 (except for DBUS read operations) is enabled
by setting RQ to “L” of. Data is taken at the rising edge of SCLK and data is output at the falling edge of
SCLK. As for the data format, command code is input first, then address and coefficient data is input or
output. Since a single command is completed by setting RQ to “H”, in order to write a new command, it
is necessary to set RQ to low again after setting RQ to “H”.
Contrarily, DBUS data reads are of accomplished by setting RQ to “H” (no command code input ).
There is a case where SI is used as control signal, depending upon the application. In this case, this pin
should be protected spurious noise, as is the case of a normal clock signal..
Command Code table is listed below.
Conditions Code name
Command code
Remark
for use
WRITE READ
RESET
Phase
CONT0
CONT1
CONT2
60h
70h
For the function of each bit,
62h
72h
See the description of Control
64h
74h
Registers
CONT3
66h
76h
CONT4
68h
78h
CONT5
6Ah
7Ah
CONT6
6Ch
7Ch
CONT7
-
DCh
PRAM
C0h
C1h
CRAM
A0h
A1h
OFRAM
90h
91h
External condition jump
C4h
-
CRC check (R(x))
B6h
D6h
Hands free parameter
E0h
E1h
RUN
phase
CONT0∼CONT7
NA
above Read available, same as RESET code.
address
CRAM rewrite preparation A8h
-
It needs to do before CRAM rewrite
CRAM rewrite
A4h
-
OFRAM rewrite preparation 98h
-
It needs to do before OFRAM rewrite
OFRAM rewrite
94h
-
External condition jump
C4h
-
Same code as RESET
CRC check (R(x))
B6h
D6h
Same code as RESET
note: As there are some duplicated codes in use, command codes other than those listed above should not
be accessed, as erroneous operation may result. If no communication exists with a microprocessor, set
SCLK to “H” and SI to “L”.
[MS0296-E-00]
49
2005/03