AK7750 Datasheet, PDF (45/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
(5) About Clock Changes
Changes to CKS1, CKS0, CKSX or SMODE are made during the system reset ( S_RESET = “L”,
INIT_RESET = “H”), or when an input clock is switched ( XTI @ CKSX= “H” or BITCLK (_I ) @ ( CKSX =
“L” & SMODE = “L”)). A clock reset is made using either the CK_RESET pin or by using CKRST control
register bit. After a reset, the internal Master clock, MCLK, is stopped and it is safe to change settings
(MCLK = 36.864 MHz or 33.8688 MHz) during the system reset.
After executing a system reset, clock reset is performed by changing the CK_RESET pin from “H” to “L”,
and by continuously supplying a clock- for a duration of longer than 120 / MCLK [us] from the falling edge
of CK_RESET ( S_RESET and CK_RESET pins can be simultaneously set to low ). When the CKRS
control register is used, the duration is 120 / MCLK [us] from the rising edge of 16th clock of CONT0.
Pin setting and input clock changes (XTI @ CKSX = “H” or BITCLK (_I) @ (CKSX = “L” & SMODE = “L”)
should be done after MCLK is stopped.
After changes are made and after the input clock is stabilized to the new value, release CK_RESET from
“L” to “H” and PLL is restarted.
Do not transmit the DSP program and coefficient data from the microprocessor until the PLL reaches stable
oscillation (about 25ms). Control register read/write operations are allowed after the input clock is stabilized
to the new value.
The AK7750 returns to normal operating condition by rising S_RESET to “H” after the DSP program
and coefficient data are transmitted. When pin-set- and clock input switches are made and µC interface is
not used, it is possible to raise both the CK_RESET and S_RESET pins simultaneously to return the
AK7750 to normal operation. However an internal circuit reset cannot be released until the PLL reaches its
stable oscillation (about 25ms) even if S_RESET is released.
S_RESET
CK_RESET
XTI
tCKFCK
pin setting
clock change
new input
clock is stable
PLLis stable
(about 25ms)
download
DSP program
read/write control register
Figure CK_RESET Sequence
XTI
mode
0
1
2
3
tCKFCK table(XTI mode)
CKS
[1:0] XTI
0h MCLK/3
1h MCLK/2
2h MCLK*(2/3)
3h MCLK
XTI cycles
40
60
80
10
BCK
mode
0
1
2
3
tCKFCK table(BCK mode)
CKS
[1:0] BITCLK
0h MCLK/12
1h MCLK/6
2h MCLK/3
3h MCLK/72
BITCLK cycles
10
20
40
10
tCKFCK(min)
fs:48kHz series
3.3µs
3.3µs
3. 3µs
0.3µs
fs:44.1kHz series
3.6µs
3.6µs
3.6µs
0.3µs
tCKFCK(min)
fs:48kHz series
3.3µs
3.3µs
3.3µs
19.5µs
fs:44.1kHz series
3.6µs
3.6µs
3.6µs
NA
[MS0296-E-00]
45
2005/03