AK7750 Datasheet, PDF (27/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
Functional Description
( 1 ) Various Pin Setting
1) CKS1,CKS0 : Master Clock ( MCLK ) Set pin
CKSX : Master Clock Select pin
The AK7750 usually operates using a 36.864 MHz Master Clock (MCLK) (or 33.8688 MHz). When CKSX =
“H”, the XTI input clock is selected by the CKS1 and CKS0 pins.
In addition to the normal use described above, the AK7750 can also operate using BITCLK-I or BITCLK as
a master clock input during slave mode operation (SMODE = “L”) by setting CKSX = “L”.
Since the AK7750 is running in slave mode instead of master mode, certain modes may not be available
since the AK7750 modes are restricted by the incoming audio clock.
„ Mode setting by CKSX, CKS1, CKS0 pins
a ) XTI selection at CKSX = “H”
XTI CKS
XTI
fs: sampling frequency
Internal
mode [1:0] XTI
Fs:48kHz series fs:44.1kHzseries
0
0h MCLK/3
12.288MHz
11.2896MHz
1
1h MCLK/2
18.432MHz
16.9344MHz
2
2h MCLK*(2/3)
24.576MHz
22.5792MHz
3
3h MCLK
36.864MHz
33.8688MHz
note) CKS1 = CKS[1],CKS0 = CKS[0]
A crystal oscillator cannot be used in XTI mode 3.
For hands-free mode, use fs = 48 KHz.
PLL
use
use
use
not use
Sample-rate setting is performed using the (CONT0) control register.
Usually XTI modes 0 and 1 are used (XTI mode 0 is selected when CKS1 and CKS0 pins are left open).
XTI mode 2 is only used when a 512 fs clock is available externally. XTI mode 3 is used when the PLL is
not used.
To change clock settings after power on (CKS1, CKS0 and CKSX),an initial reset ( INIT_RESET = “L”,
S_RESET = “L”), or during a clock reset ( CK_RESET = “L”, S_RESET = “L”) should be performed.
Since the PLL circuit and internal clocks are controlled by CKS1, CKS0 and CKSX pins, an erroneous
operation may occur if any pin setting changes occur under any conditions other than those described
above (same conditions apply when changing the input for XTI).
A reset can be performed using either the pin CK_RESET or the CKRST bit (CONT0:D1) in control
register. When using the register RESET, the CK_RESET pin should be set to “H” or should be linked
together with INIT_RESET pin.
CK_RESET (pin)
CKRST(reg.)
CK_RESET
(H:RESET)
CK_RESET (pin) and CKRST(reg.) relation
[MS0296-E-00]
27
2005/03