AK7750 Datasheet, PDF (56/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
2) Read during reset phase
a) Control register data read (during reset phase)
Control Register Read operations (at reset) are executed in 16-bit SCLK clocks.
Control register values D7 ~ D1 are output at the falling edge of SCLK after command code is input. D0
is invalid, ignore this bit.
Data transfer procedure
c Command code
70h, 72h, 74h, 76h, 78h, 7Ah, 7Ch, D8h, DAh, DCh
note) 50h,54h,58h are not usable as they are dedicated for testing.
For each bit function, please refer to section (2) Control Register Settings.
S_RESET
RQ
SCLK
SI
70h(example)
74h(example)
SO
D7yyyyD1
D7yyyyD1
Reading of control register data
[MS0296-E-00]
56
2005/03