AK7750 Datasheet, PDF(40/77 Page) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

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AK7750 Datasheet, PDF (40/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

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[ASAHI KASEI]

[AK7750]

6) CONT5 : HF Set & Instruction Set

The setting is enabled only during the system reset ( S_RESET = âLâ ).

Command

Name

Code

Write Read

6Ah

7Ah

CONT5 HF_RST_N HF

PID SSDIN4 SSDIN3 OP1

OP0

c D7: HF_RST_N

0: reset the ARM for hands-free use.

1: release the reset of the ARM for HF use.

D0 Default

0000_000x

Set HF-RST-N = 1 and after the system reset is released, it is put into hands-free mode.

In order to return from the hands-free mode to normal DSP mode, set HF-RST-N = 0.

d D6: HF

0: normal mode set

1: hands-free mode set

DSP_SDIN3 and DSP_SDOUT3 are switched to the ARM interface.

SDIN3 cannot be used (can be used as JX1). Output of PIN-SDOUT3 becomes âLâ.

e D5: PID Selection of hands-free parameters sets

0 : ROM data is used (Default set of hands-free parameters)

1 : Param Register RAM is used

Noise canceller uses the customized parameter set which is allocated in RAM area. The

procedure for getting the optimized hands-free parameters is described in the page <TBD>.

f D4: SSDIN4 Selection of DSP instrcution

0 : ODRB*,MSRG*

1 : INL4*, INR4*(SDIN4 Digital Input)

This bit switches the source of DBUS from ODRB*, MSRG* to INL4*, INR4*.

(*: ODRB, MSRG, INL4, INR4 are assembler code. Please see other document for the detail)

g D3: SSDIN3 Selection of DSP instruction

0 : TDR2*, TDR3* (DR2, DR3 Through Output)

1 : INL3*, INR3* (SDIN3 Digital Input)

This bit switches the source of DBUS from TDR2*, TDR3* to INL3*, INR3*.

(*: TDR2, TDR3, INL3, INR3 are assembler code. Please see other document for the detail)

h D2, D1 : OP1, OP0 Offset- RAM- Pointer Mode Select

mode OP1

OP0

Pointer 1

Pointer 0

DBUS immediate pointer OFFSET indirect pointer

OFFSET indirect pointer OFFSET indirect pointer

DBUS immediate pointer DBUS immediate pointer

N/A

note) Even when DLC* is issued in mode 1, the offset address (location) is valid.

(*: DLC is assembler code. Please see other document for the detail)

i D0 : set â0â.

note) Under-lined set values in c ~h above indicate the default values.

[MS0296-E-00]

2005/03

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