AK7750 Datasheet, PDF (44/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
(4) About Reset
The AK7750 has 3 reset pins, INIT_RESET , S_RESET and CK_RESET .
There are 2 reset bits in control registers HF_RESET_N (CONT5 D7) and CKRST (CONT0 D1).
A clock reset CK_RESET (CKRST) will be described in section (5) , “Switching Clocks”.
When the CK_RESET pin is not used, either connect it to the INIT_RESET pin or set it to “H”.
HF_RESET_N is described in section (2) “Control Register Settings”.
INIT_RESET is used to initialize the AK7750 as is described in the Power-on Sequence description.
When changing CKS1, CKS0, CKSX or SMODE, or when changing the XTI pin’s input clock frequency, it is
recommended to execute it during the initial reset ( INIT_RESET = “L”, S_RESET = “L” ). A change can
be made during a clock reset ( CK_RESET , CKRST) if audio interruption is acceptable and no other
setting changes are made.
Since the CKS1, CKS0, CKSX, SMODE and XTI pins are involved in PLL and internal clock control,
erroneous operation may occur if any changes are made other than during initial reset or clock reset.
With INIT_RESET = “H” & S_RESET = “L”, the device is put into system reset condition (“ reset
“implies a system reset ).
Usually program and RAM data is written during a system reset (excluding write during RUN).
During a system reset, both the ADC and DAC are reset. The REF generating circuit remains in operation.
CLKO output and LRCLK, BITCLK in Master mode are stopped during a system reset.
System reset is released by rising S_RESET to “H”, which starts the internal counters.
In Master mode, LRCLK and BITCLK are generated by the AK7750’s counters, which may generate a
clock conflict if other devices are not properly initialized. In Slave mode, when a system reset is released,
internal timing starts to operate in sync with the rising edge of LRCLK ( in standard input format ).
Timing adjustment between an external clock and internal timing is made during this time. During the
operation, if the phase-difference (both at the rising edge and at the falling edge) between LRCLK and
internal timing is within 2 clock pulses of BITCLK (64fs), operation continues.
When the phase-difference becomes larger than the above range, a phase adjustment is made in sync with
the rising edge of LRCLK ( in standard input format ).
This circuit protects the AK7750 from becoming out of sync with external circuits due to noise etc. Correct
data is not output for a while even after out-of-sync condition returns to normal.
In the ADC, data output is available 516 LRCLK clocks after the internal counters start to operate (internal
counters start to operate right after the release of system reset in Master mode, or in Slave mode
approximately 2 LRCLK clocks after the release of system reset).
The AK7750 returns to normal operation at the rising edge of S_RESET .
The AK7750 goes from normal state to system reset state by the falling edge of S_RESET . Please do
not stop the input clock for 3 MCLK times period after the falling edge of S_RESET .
[MS0296-E-00]
44
2005/03