AK7750 Datasheet, PDF (34/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
( 2 ) Control Register Settings
In the AK7750, control registers are programmed via the microprocessor interface. There are 8 registers in
total. Each register is configured with 7 bits, but SCLK always requires 16 bit data clocks (8 bits for
Command Code and 8 bits for DATA ).
The Register configuration is listed below. Each control register value is set when D0 is written.
Control register writes are performed during a system reset ( S_RESET = “L” ), but reads can be
performed at any time during normal chip operation.
Control registers are initialized by an INIT_RESET = “L”. They are not initialized by a system reset
( S_RESET = “L” ).
TEST: for testing purpose (set to “0” )
X: The value “0” must be set with a write operation. Failure to do say will result in an unknown value during
a read operation.
Command Name D7
Code
D6
D5
D4
D3
D2
D1
D0 Default
WR
60h 70h CONT0 DFS2
DFS1]
DFS0
DIF2
DIF1
DIF0
CKRST
X 0000_000x
62h 72h CONT1 DATARAM RM
BANK1
BANK0
CMP_N
SS1
SS0
X 0000_000x
64h 74h CONT2 PSAD
OUT3E_N OUT2E_N OUT1E_N NRDY
TEST
TEST
X 0000_000x
66h 76h CONT3 SWJX2
SWJX1
SWJX0_N SWQ4
SWIA
SWQD SWEE
X 0000_000x
68h 78h CONT4 TEST
CLKS1
CLKS0
CLKE_N BLCKE_N OUT4E TEST
X 0000_000x
6Ah 7Ah CONT5 HF_RST_N HF
PID
SSDIN4 SSDIN3 OP1
OP0
X 0000_000x
6Ch 7Ch CONT6 PSCODEC DAF
SF1
SF0
SMUTE
TEST
TEST
X 0000_000x
(PLLSTBY)
- DCh CONT7 SRRQ
CRCL
TEST
TEST
TEST
TEST
TEST
X 0000_000x
Note) Do not write other data values or addresses.
1. In order to prevent erroneous operation, write to the CONT0 and CONT5 registers only during a system
reset ( S_RESET = “L”).
2. It is recommended that CONT1 ~ CONT4, CONT6 ~ CONT7 registers are also only written to at a
system reset ( S_RESET =”L”).
3. TEST means for testing, and 0 should be written.
4. Default means an initialized value, to which register is initialized by INIT_RESET = “L”.
[MS0296-E-00]
34
2005/03