AK7750 Datasheet, PDF (54/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
e) External conditional jump code write (during reset phase)
External conditional jump code writes are made after all necessary operations, such as program downloads,
etc. are executed. Code writes are done in 2 bytes/set data. It is possible to input during both reset and in
normal operation mode. Input data is set at each assigned register at the rising edge of LCRLK. RDY pin
becomes “L” . After all data is transferred and it becomes “H” when write operation is finished.
External jump codes are 8-bits long and when any bit among the 11 code bits of JX0, JX1 and JX2 input
pins and any single bit of “1” in the IFCON field match, the jump instruction is executed.
When writing data during the reset, it can be executed only before reset is released after completing all
data transfers.
Setting RQ from “L” to “H” during reset mode writes should be made more than 2 MCLK clocks after
reset is released. RDY becomes “H” when the next rising edge of LRCLK is detected.
Write operations from the microprocessor are inhibited until RDY becomes “H”.
The IFCON field is an external condition, written in the DSP program.
This jump code is reset to 00h by setting INIT_RESET to “L”, however, it remains at its previous condition
even when S_RESET =”L”.
Note: It should be noted that the LRCLK phase is inverted in the I2S-compatible state.
7
0 JX0 JX1 JX2
External condition code „ „ „ „ „ „ „ „ † † †
Check if any bit of a single “1” bit between the assigned bit by IFCON
and external jump code
IFCON field
16
9876
‹‹‹‹‹‹‹‹‹‹‹
Data transfer procedure
c Command code
d Code data
C4h ( 1 1 0 0 0 1 0 0)
(D7 . . . . . D0)
S_RESET
SCLK
SI
SO
RQ
LRCLK
RDY
11000100 D7••••D0
L ch
R ch
2LRCLK(max)
External conditional jump write operation timing (during reset phase)
[MS0296-E-00]
54
2005/03