AK7750 Datasheet, PDF (28/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
b) BITCLK(_I ) Selection at CKSX = “L” ( SMODE = “L” )
EESEL=”L”
BCK CKS
mode [1:0]
0 0h
1 1h
2 2h
3 3h
BITCLK_I
BITCLK_I
MCLK/12
MCLK/6
MCLK/3
MCLK/72
(64fs)
sample rate
standard speed
double speed
4X speed
fs=8kHz
fs: sampling frequency
@SMODE=”L”
fs:48kHz series
3.072MHz
6.144MHz
12.288MHz
512kHz
fs:44.1kHz series
2.8224MHz
5.6448MHz
11.2896MHz
-
Internal
PLL
use
use
use
use
EESEL=”H”
BCK CKS
BITCLK
(64fs)
@SMODE=”L”
Internal
mode [1:0] BITCLK
0 0h MCLK/12
1 1h MCLK/6
2 2h MCLK/3
3 3h MCLK/72
sample rate
fs:48kHz series fs:44.1kHz series PLL
standard speed
3.072MHz
2.8224MHz
use
double speed
6.144MHz
5.6448MHz
use
4x speed
12.288MHz
11.2896MHz
use
fs=8kHz
512kHz
-
use
note1) CKS1 = CKS[1],CKS0 = CKS[0]
note2)BITCLK_I clock is selected at EESEL = “L” and BITCLK clock is selected at EESEL = “H”.
note3) Hands-free mode is available only when BCK mode 3 is selected.
BCK modes are also used to generate internal master clock other than used as a primary bit clock.
Therefore some limitations exist when to use BITCLK (_I) (for details, please refer to item b) of the Clock
Source description).
BCK mode is not available when the device operates at master mode.
The sampling rate is fixed by BCK mode that is not affected by the speed setting (standard speed,
double speed, and 4x speed) of the control register.
Both of internal ADC and DAC are not available when BCK mode 1or 2 is selected. PSAD(D7) bit in
CONT2 register and PSCODEC(D7) bit in the CONT6 register should be set to “1”.
Please set XTI = “L” when XTI is not used at all.
When to switch setting of CKS1, CKS0 and CKSX after the power-on, it should be done either during the
initial reset ( INIT_RESET = “L”, S_RESET = “L” ) or during the clock reset ( CK_RESET = “L”,
S_RESET = “L” ). Since PLL circuit and internal clocks are controlled by CKS1, CKS0 and CKSX pins,
an erroneous operation may occur if any pin set change is taken place under any conditions other than
those described above (same conditions apply when to change input BITCLK(_I)).
Instead of CK_RESET , D1 bit in control register (CONT0: D1 ) can be used. In this case, CK_RESET
pin should be set to “H” or should be linked together with INIT_RESET pin.
CK_RESET (pin)
CKRST(reg.)
CK_RESET
(H:RESET)
CK_RESET (pin) and CKRST(reg.) relation
[MS0296-E-00]
28
2005/03