AK7750 Datasheet, PDF (57/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
b) Program RAM read (during reset phase)
Program RAM reads require inputting a command code and address to be accessed and setting SCLK to
fall after setting SI to “H”. The output data is synchronized with the falling edge of SCLK (Ignore RDY
signal). When the requested read addresses are in consecutive locations, repeat the above procedure
again by setting SI to “H”.
Data transfer procedure
cCommand code input C1h ( 1 1 0 0 0 0 0 1 )
dRead address input MSB ( 0 0 0 0 0 0 A9 A8)
eRead address input LSB (A7 . . . . . . A0)
S_RESET
RQ
SCLK
SI
SO
RDY
11000001 000000 A9A8 A7yyyy A1 A0
D31yyyyD0 D31yyyyD0
CRAM Data Read
[MS0296-E-00]
57
2005/03