HMC7043 Datasheet, PDF (6/44 Pages) Analog Devices – JEDEC JESD204B support

Data Sheet
HMC7043
ADDITIVE JITTER AND PHASE NOISE CHARACTERISTICS
Table 5.
Parameter¹
ADDITIVE JITTER
RMS Additive Jitter
Min Typ Max
<30
<15
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise
Offset = 1 MHz
Offset = 10 MHz
Offset = 20 MHz
−144.3
−154.8
−155.2
Unit
fs rms
fs rms
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
HMC7044 used as a clock source (see Figure 3)
Clock output frequency (fCLKOUT) = 983.04 MHz, BW = 12 kHz to 20 MHz,
clock input slew rate ≥ 8 ns
fCLKOUT = 2457.6 MHz, BW = 12 kHz to 20 MHz, clock input slew rate ≥ 4 ns
HMC830 used as a clock source and configured to produce 983.04 MHz
at the output (see Figure 4), input slew rate > 1 V/ns
fCLKOUT = 983.04 MHz, fCLKOUT = 983.04 MHz, divide by 1 at the output
fCLKOUT = 983.04 MHz, fCLKOUT = 2949.12 MHz, divide by 3 at the output
fCLKOUT = 983.04 MHz, fCLKOUT = 983.04 MHz, divide by 1 at the output
1 _{Guaranteed by design and characterization.}
CLOCK OUTPUT DISTRIBUTION SPECIFICATIONS
Table 6.
Parameter
Min
CLOCK OUTPUT SKEW
CLKOUTx/CLKOUTx to SCLKOUTx/SCLKOUTx Skew
Within One Clock Output Pair
Any CLKOUTx/CLKOUTx to Any SCLKOUTx/SCLKOUTx
PROPAGATION DELAY CLKIN to CLKOUTx and SCLKOUTx¹ 770
CLOCK OUTPUT DIVIDER CHARACTERISTICS
12-Bit Divider Range
1
SYSREF CLOCK OUTPUT DIVIDER CHARACTERISTICS
12-Bit Divider Range
1
CLOCK OUTPUT ANALOG FINE DELAY
Analog Fine Delay
Adjustment Range¹
135
Resolution
Maximum Analog Fine Delay Frequency
CLOCK OUTPUT COARSE DELAY (FLIP FLOP BASED)
Coarse Delay Adjustment Range
0
Coarse Delay Resolution
Maximum Frequency Coarse Delay
CLOCK OUTPUT COARSE DELAY (SLIP BASED)
Coarse Delay
Adjustment Range
Resolution
Maximum Frequency Coarse Delay
Typ Max Unit
15
|ps|
30
|ps|
820 870 ps
4094
4094
Test Conditions/Comments
Same pair, same type termination and
configuration
Any pair, same type termination and
configuration
fCLKIN = 983.04 MHz, all VCC set to 3.3 V
1, 3, 5, and all even numbers up to 4094
1, 3, 5, and all even numbers up to 4094;
pulse generator behavior is only
supported for divide ratios ≥ 32
670 ps
25
ps
1600
MHz
24 delay steps, fCLKOUT = 983.04 MHz
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
17
169.54
1500
½ CLKIN period
ps
MHz
17 delay steps
fCLKIN = 2949.12 MHz
1 to ∞
339.08
1600
CLKIN period
ps
MHz
fCLKIN = 2949.12 MHz
1 _{Guaranteed by design and characterization.}
Rev. B | Page 5 of 43