HMC7043 Datasheet, PDF (41/44 Pages) Analog Devices – JEDEC JESD204B support

HMC7043
Data Sheet
Address
0x00CE, 0x00D8, 0x00E2,
0x00EC, 0x00F6, 0x0100,
0x010A, 0x0114, 0x011E,
0x0128, 0x0132, 0x013C,
0x0146, 0x0150
0x00CF, 0x00D9, 0x00E3,
0x00ED, 0x00F7, 0x0101,
0x010B, 0x0115, 0x011F,
0x0129, 0x0133, 0x013D,
0x0147, 0x0151
0x00D0, 0x00DA, 0x00E4,
0x00EE, 0x00F8, 0x0102,
0x010C, 0x0116, 0x0120,
0x012A, 0x0134, 0x013E,
0x0148, 0x0152
1 _{X means don’t care.}
Bits Bit Name
Settings¹ Description
[7:4] Reserved
Reserved.
[3:0] 12-Bit Multislip
Digital Delay[11:8]
(MSB)
12-bit multislip digital delay amount MSB.
[7:2] Reserved
[1:0] Output Mux
Selection[1:0]
00
01
10
11
[7:6] Idle at Zero[1:0]
00
01
10
11
5
Dynamic driver
enable
0
1
[4:3] Driver Mode[1:0]
00
01
10
11
2
Reserved
[1:0] Driver
Impedance[1:0] ₀₀
01
10
11
Reserved.
Channel output mux selection.
Channel divider output.
Analog delay output.
Other channel of the clock group pair.
Input clock (fundamental). Fundamental can also be
generated with 12-bit channel divider ratio = 1.
Idle at Logic 0 selection (pulse generator mode only).
Force to Logic 0 or VCM.
Normal mode (selection for DCLK).
Reserved.
Force to Logic 0.
Force outputs to float, goes naturally to VCM.
Dynamic driver enable (pulse generator mode only).
Driver is enabled/disabled with channel enable bit.
Driver is dynamically disabled with pulse generator events.
Output driver mode selection.
CML mode.
LVPECL mode.
LVDS mode.
CMOS mode.
Reserved.
Output driver impedance selection for CML mode.
Internal resistor disable.
Internal 100 Ω resistor enable per output pin.
Reserved.
Internal 50 Ω resistor enable per output pin.
Access
RW
RW
RW
Rev. B | Page 40 of 43