HMC7043 Datasheet, PDF (42/44 Pages) Analog Devices – JEDEC JESD204B support

Data Sheet
APPLICATIONS INFORMATION
EVALUATION PCB AND SCHEMATIC
For the circuit board in this application, use RF circuit design
techniques. Ensure that signal lines have 50 Ω impedance.
Connect the package ground leads and exposed paddle directly
to the ground plane similar to that shown in Figure 32 and
Figure 33. Use a sufficient number of via holes to connect the
top and bottom ground planes. The evaluation circuit board is
available from Analog Devices, Inc., upon request.
The typical Pb-free reflow solder profile shown in Figure 31 is
based on JEDEC J-STD-20C.
HMC7043
RAMP UP
3°C/SECOND MAX
217°C
60 TO 150
SECONDS
260 – 5/0°C
150°C TO 200°C
RAMP DOWN
6°C/SECOND MAX
60 TO 180
SECONDS
480 SECONDS MAX
TIME (Second)
20 TO 40
SECONDS
Figure 31. Pb-Free Reflow Solder Profile
Figure 32. Evaluation PCB Layout, Top Side
Rev. B | Page 41 of 43