HMC7043 Datasheet, PDF (21/44 Pages) Analog Devices – JEDEC JESD204B support

HMC7043
Data Sheet
Table 13. Multislip Configuration
Bit Name
Description
Multislip Enable
Allow multislip. This bit determines whether the 12-Bit Multislip Digital Delay[11:0] parameter is used
for multislip operations. Note that a multislip operation is automatically started following a SYNC or
pulse generator initiation if multislip enable = 1.
12-Bit Multislip Digital Delay[11:0]
Multislip amount. If multislip enable = 1, any slip events (caused by GPI, SPI, SYNC, or pulse generator
events) repeat the number of times set by 12-Bit Multislip Digital Delay[11:0] to adjust the phase by the
multislip amount × clock input cycles. A value of 0 is not supported if multislip enable = 1. Note that
phase slips are free from a noise and current perspective, that is, no additional power is needed and
with no noise degradation, but they take some time to occur. Each slip operation takes a number of
nanoseconds to complete, and thus the phases do not necessarily stabilize immediately. An alarm is
available for the user to indicate when all phase operations are complete.
Table 14. Typical Configuration Combinations
Bit Name
DCLK
12-Bit Channel Divider[11:0] Small
Start-Up Mode-Bit
Normal
Fine Analog Delay[4:0]
Off
Coarse Digital Delay[4:0]
Optional
Slip Enable
Optional
Multislip Enable
Optional
High Performance Mode
Optional
Sync Enable
On
Dynamic Driver Enable
Don’t care
Force Mute[1:0]
Don’t care
Pulse Generator SYSREF
Big
Pulse generator
Optional
Optional
Optional
Off
Off
On
On
On
Manual SYSREF
Big
Normal
Optional
Optional
Optional
Optional
Off
On
Don’t care
Don’t care
NonJESD204B
Any
Normal
Off
Optional
Optional
Optional
Optional
Optional
Don’t care
Don’t care
Synchronization FSM/Pulse Generator Timing
Figure 25 show a block diagram of the interface of the SYNC/
pulse generator control to the divider channels and the internal
SYSREF timer.
The SYSREF timer counts in periods defined by SYSREF
Timer[11:0], a 12-bit setting from the SPI. The SYSREF
timer sequences the enable, reset, and startup, and disables
the downstream dividers in the event of sync or pulse generator
requests. Program the SYSREF timer count to a submultiple of
the lowest output frequency in the clock network, and never
faster than 4 MHz. To synchronize the divider channels, it is
recommended, though not required, that the SYSREF Timer[11:0]
bits be set to a related frequency that is either a factor or
multiple of other frequencies on the IC.
The pulse generator is defined with respect to the periods of
this SYSREF timer, not with respect to the output period. This
behavior of the pulse generator leads to a timing constraint that
must be considered to prevent any runt pulses from affecting
the pulse generator stream.
Figure 27 shows the start-up behavior of an example divider
that is configured as a pulse generator, with a period matching
the internal SYSREF period.
The startup of the pulse stream occurs a fixed number of clock
input cycles after the FSM transitions to the start phase. Disabling
the pulse generator stream where the logic path is forced to zero
comes from a combinational path directly from the FSM.
Because the divider has the option for nearly arbitrary phase
adjustment, the stop condition can arrive when the pulse stream
is a Logic 1 and create a runt pulse.
For phase offsets of zero to (50% − 8) clock input cycles, and at
clock input frequencies <3 GHz, this condition is met naturally
within the design. For clock input frequencies >3 GHz, it is
recommended to use digital delay or slip offsets to increase the
natural phase offset and avoid the stress conditions.
The situation is avoided by never applying phase offset more
than (50% − 8) clock input cycles to an output channel
configured as a pulse generator.
Rev. B | Page 20 of 43