HMC7043 Datasheet, PDF (24/44 Pages) Analog Devices – JEDEC JESD204B support

Data Sheet
Output Buffer Details
NORTHWEST
NORTHEAST
HMC7043
CLKOUT0
CLKOUT0
SCLKOUT1
SCLKOUT1
RESET
BGAPBYP1
LDOBYP2
VCC1_
CLKDIST
SCLKOUT3
SCLKOUT3
CLKOUT2
CLKOUT2
SCLKOUT9
SCLKOUT9
GPIO
SPI
VCC5_
SYSREF
RFSYNCIN
RFSYNCIN
VCC4_
CLKIN
CLKIN
CLKIN
SOUTHWEST
SOUTH
Figure 28. Clock Grouping
Figure 28 shows the clock groups by supply pin location on the
the user to identify quickly that the desired SYSREF and device
package. With appropriate supply pin bypassing, the spurious
clock states are presented at the outputs of the HMC7043.
noise of the outputs is improved.
The user has the flexibility to assign the SYSREF valid interrupt to
Table 15 describes how the supply pins of each of the 14 clock
a GPO pin or to use a software flag, set via Register 0x007D, Bit 2,
channels are connected within the seven clock groups. Clock
which the user may poll as necessary. The flag notifies the user
channels that are closest to each other have the best channel to
when the system is configured and operating in the desired
channel skew performance, but they also have the lowest isolation
state, or conversely when it is not ready.
from each other. Select critical signals that require high isolation
from each other from groups with distant supply pin locations.
An example of the expected isolation and channel to channel
skew performance of the HMC7043 at 1 GHz is provided in
TYPICAL PROGRAMMING SEQUENCE
To initialize the HMC7043 to an operational state, use the
following programming procedure:
Table 16.
1. Connect the HMC7043 to the rated power supplies. No
SYSREF Valid Interrupt
One of the challenges in a JESD204B system is to control and
minimize the latency from the primary system controller IC,
typically an ASIC or FPGA, to the data converters. To estimate
the correct amount of latency in the system, the designer must
know the time required for a master clock generator like the
HMC7043 to provide the correct output phases at each output
channel after receiving the synchronization request. Typically, a
period of time is required on the device to implement the
change requests on the outputs due to internal state machine
cycles, data transfers, and any propagation delays. The SYSREF
valid interrupt is a function to notify the user that the correct
output settings and phase relationships are established, allowing
specific power supply sequencing is necessary.
2. Release the hardware reset by switching from Logic 1 to
Logic 0 when all supplies are stable.
3. Load the configuration updates (provided by Analog
Devices, Inc.) to specific registers (see Table 40).
4. Program the SYSREF timer. Set the divide ratio (a submultiple
of the lower output channel frequency). Set the pulse
generator mode configuration, for example, selecting the
level sensitivity option and the number of pulses desired.
5. Program the output channels. Set the output buffer modes
(for example, LVPECL, CML, and LVDS). Set the divide
ratio, channel start-up mode, coarse/analog delays, and
performance modes.
6. Ensure the clock input signal are provided to CLKIN.
Rev. B | Page 23 of 43