HMC7043 Datasheet, PDF (11/44 Pages) Analog Devices – JEDEC JESD204B support

HMC7043
Data Sheet
Pin No.
27
28
29
30
31
32
33
34
35
36
37
38
39
Mnemonic
VCC4_CLKIN
RFSYNCIN
RFSYNCIN
VCC5_SYSREF
SLEN
SCLK
SDATA
GPIO
SCLKOUT9
SCLKOUT9
CLKOUT8
CLKOUT8
VCC6_OUT
40
CLKOUT10
41
CLKOUT10
42
SCLKOUT11
43
SCLKOUT11
44
SCLKOUT13
45
SCLKOUT13
46
CLKOUT12
47
CLKOUT12
48
VCC7_OUT
EP
Type¹
P
I
I
P
I/O
I/O
I/O
I/O
O
O
O
O
P
O
O
O
O
O
O
O
O
P
Description
Power Supply for the Clock Input Path.
True RF Synchronization Input with Deterministic Delay.
Complementary RF Synchronization Input with Deterministic Delay.
Power Supply for Common SYSREF Divider.
SPI Latch Enable.
SPI Clock.
SPI Data.
Programmable General-Purpose Input/Output.
True Clock Output Channel 9. Default SYSREF profile.
Complementary Clock Output Channel 9. Default SYSREF profile.
True Clock Output Channel 8. Default DCLK profile.
Complementary Clock Output Channel 8. Default DCLK profile.
Power Supply for Clock Group 3 (North)—Channel 8, Channel 9, Channel 10, and Channel 11. See the
Clock Grouping, Skew, and Crosstalk section.
True Clock Output Channel 10. Default DCLK profile.
Complementary Clock Output Channel 10. Default DCLK profile.
True Clock Output Channel 11. Default SYSREF profile.
Complementary Clock Output Channel 11. Default SYSREF profile.
True Clock Output Channel 13. Default SYSREF profile.
Complementary Clock Output Channel 13. Default SYSREF profile.
True Clock Output Channel 12. Default DCLK profile.
Complementary Clock Output Channel 12. Default DCLK profile.
Power Supply for Clock Group 0 (Northwest)—Channel 0, Channel 1, Channel 12, and Channel 13. See
the Clock Grouping, Skew, and Crosstalk section.
Exposed Pad. Connect the exposed pad to a high quality RF/dc ground.
1 _{O is output, I is input, P is power, R is reserved, and I/O is input/output.}
Rev. B | Page 10 of 43