HMC7043 Datasheet, PDF (17/44 Pages) Analog Devices – JEDEC JESD204B support

HMC7043
Data Sheet
DETAILED BLOCK DIAGRAM
CLKOUT0
CLKOUT0
SCLKOUT1
SCLKOUT1
CLKOUT2
CLKOUT2
SCLKOUT3
SCLKOUT3
CLKOUT4
CLKOUT4
SCLKOUT5
SCLKOUT5
CLKOUT6
CLKOUT6
SCLKOUT7
SCLKOUT7
ANALOG
MUX DELAY
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
MUX ANALOG
DELAY
ANALOG
MUX DELAY
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
MUX ANALOG
DELAY
ANALOG
MUX DELAY
COARSE _DIVIDER CYCLE
DIGITAL
DELAY
(1 TO 4094)
SLIP/
SYNC
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
MUX ANALOG
DELAY
ANALOG
MUX DELAY
COARSE _DIVIDER CYCLE
DIGITAL
DELAY
(1 TO 4094)
SLIP/
SYNC
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
MUX ANALOG
DELAY
COARSE _DIVIDER CYCLE
DIGITAL
DELAY
(1 TO 4094)
SLIP/
SYNC
FUNDAMENTAL MODE
CLK DISTRIBUTION PATH _DIVIDER
÷1, ÷2
CLKIN
CLKIN
SYSREF TIMER
SYNC/PULSOR
GPI
CONTROL
SPI
RFSYNCIN
RFSYNCIN
TO LEAF DIVIDERS
CYCLE _DIVIDER
SLIP/
SYNC
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
CYCLE _DIVIDER COARSE
SLIP/
SYNC
(1 TO 4094)
DIGITAL
DELAY
FUNDAMENTAL MODE
CYCLE _DIVIDER COARSE
SLIP/
SYNC
(1 TO 4094)
DIGITAL
DELAY
FUNDAMENTAL MODE
CYCLE _DIVIDER COARSE
SLIP/
SYNC
(1 TO 4094)
DIGITAL
DELAY
FUNDAMENTAL MODE
CYCLE _DIVIDER COARSE
SLIP/
SYNC
(1 TO 4094)
DIGITAL
DELAY
FUNDAMENTAL MODE
CYCLE _DIVIDER COARSE
SLIP/
SYNC
(1 TO 4094)
DIGITAL
DELAY
FUNDAMENTAL MODE
ANALOG
DELAY MUX
ANALOG MUX
DELAY
ANALOG
DELAY MUX
ANALOG MUX
DELAY
ANALOG
DELAY MUX
ANALOG MUX
DELAY
CLKOUT8
CLKOUT8
SCLKOUT9
SCLKOUT9
CLKOUT10
CLKOUT10
SCLKOUT11
SCLKOUT11
CLKOUT12
CLKOUT12
SCLKOUT13
SCLKOUT13
LDOs
SPI
ALARM GENERATION
DEVICE
CONTROL
BGABYP1 LDOBYP2
SDATA SCLK SLEN
GPIO
RESET
Figure 23. Detailed Block Diagram
CLOCK INPUT NETWORK
Input Termination Network—Common for All Input Buffers
The two clock and RFSYNC input buffers share similar architecture
and control features. The input termination network is configurable
to 100 Ω, 200 Ω, and 2 kΩ differentially. It is typically ac-coupled
on the board, and uses the on-chip resistive divider to set the
internal common-mode voltage, VCM, to 2.1 V.
By closing the 50 Ω termination switch (see Figure 24), the network
also can serve as the termination system for an LVPECL driver.
Although the input termination network for the two clock and
RFSYNC input buffers is identical, the buffer behind the
network is different.
2.8V
4kΩ
5kΩ
1pF
50Ω,
100Ω,
1kΩ
50Ω,
100Ω,
50Ω
1kΩ
Figure 24. On-Chip Termination Network for Clock and RFSYNC Buffers
Recommendations for Normal Use
For both buffer types, unless there are extenuating circumstances
in the application, use 100 Ω differential termination resistors
to control reflections, to use the on-chip dc bias network to set
the common mode level, and to externally ac couple the input
signals in. Do not use a receiver side dc termination of the
LVPECL signal.
Rev. B | Page 16 of 43