HMC7043 Datasheet, PDF (26/44 Pages) Analog Devices – JEDEC JESD204B support

Data Sheet
HMC7043
Table 17. Supply Network of the HMC7043 by Pin for VCC1_CLKDIST, VCC4_CLKIN, and VCC5_SYSREF
Circuit Block
Comment
Typical Current (mA)
0
VCC1_CLKDIST
Regulator to 1.8 V, Bypassed on LDOBYP2
SYSREF Timer
2
2
1
GPO Driver in High Speed Mode ²
Clock Input Distribution Network
Minimum possible value
84
8
Sync Retiming Network
Minimum possible value³
8
Subtotal for VCC1_CLKDIST
10
VCC4_CLKIN
CLKIN/CLKIN Buffer
16
CLKIN/CLKIN Path
Extra current for divide by 2
7
RFSYNCIN/RFSYNCIN⁴ Retimer
3
RFSYNCIN/RFSYNCIN Buffer
9
Subtotal or VCC4_CLKIN
0
VCC5_SYSREF
SYSREF Input Network
11
SYSREF Counter Base
12
SYSREF Counter, SYNC Network
Subtotal for VCC5_SYSREF
4
27
0
Subtotal (Without Output Paths)
10
Profile¹
1
2
2
2
1
84
34
87
36
16
16
16
16
11
12
23
0
126
52
1 _{Profile 0 is sleep mode; Profile 1 is power-up defaults, SYSREF timer running and RFSYNC buffer is disabled; Profile2 is only one clock output enabled, SYSREF timer is}
not running and RFSYNC buffer is disabled.
2 _{The current is highly dependent on rate of input/output and load of input/output traces. For heavily loaded traces, it is recommended to use a series resistance of}
~100 Ωto minimize the IR drop on the internal regulator during transitions.
3 _{A temporary current only.}
4 _{Transient current in synchronization mode, can be temporarily enabled when using external synchronization.}
Rev. B | Page 25 of 43