HMC7043 Datasheet, PDF (10/44 Pages) Analog Devices – JEDEC JESD204B support

Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HMC7043
CLKOUT0 1
CLKOUT0 2
SCLKOUT1 3
SCLKOUT1 4
RESET 5
BGAPBYP1 6
LDOBYP2 7
VCC1_CLKDIST 8
SCLKOUT3 9
SCLKOUT3 10
CLKOUT2 11
CLKOUT2 12
HMC7043
TOP VIEW
(Not to Scale)
36 SCLKOUT9
35 SCLKOUT9
34 GPIO
33 SDATA
32 SCLK
31 SLEN
30 VCC5_SYSREF
29 RFSYNCIN
28 RFSYNCIN
27 VCC4_CLKIN
26 CLKIN
25 CLKIN
NOTES
1. RSV = RESERVED PIN AND MUST BE TIED TO GROUND.
2. CONNECT THE EXPOSED PAD TO A HIGH QUALITY RF/DC GROUND.
Figure 2.
Table 9. Pin Function Descriptions
Pin No. Mnemonic
Type¹ Description
1
CLKOUT0
O
True Clock Output Channel 0. Default DCLK profile.
2
CLKOUT0
O
Complementary Clock Output Channel 0. Default DCLK profile.
3
SCLKOUT1
O
True Clock Output Channel 1. Default SYSREF profile.
4
SCLKOUT1
O
Complementary Clock Output Channel 1. Default SYSREF profile.
5
RESET
I
Device Reset Input. Active high. For normal operation, set RESET to 0.
6
BGAPBYP1
Band Gap Bypass Capacitor Connection. Connect a 4.7 µF capacitor to ground. This pin affects all
internally regulated supplies.
7
LDOBYP2
LDO Bypass 2. Connect a 4.7 µF capacitor to ground. The internal digital supply is 1.8 V. This pin is the
LDO bypass for the SYSREF section.
8
VCC1_CLKDIST P
3.3 V Supply for CLK Distribution.
9
SCLKOUT3
O
True Clock Output Channel 3. Default SYSREF profile.
10
SCLKOUT3
O
Complementary Clock Output Channel 3. Default SYSREF profile.
11
CLKOUT2
O
True Clock Output Channel 2. Default DCLK profile.
12
CLKOUT2
O
Complementary Clock Output Channel 2. Default DCLK profile.
13
VCC2_OUT
P
Power Supply for Clock Group 1 (Southwest)—Channel 2 and Channel 3. See the Clock Grouping,
Skew, and Crosstalk section.
14
RSV
R
Reserved Pin. This pin must be tied to ground.
15
SCLKOUT5
O
True Clock Output Channel 5. Default SYSREF profile.
16
SCLKOUT5
O
Complementary Clock Output Channel 5. Default SYSREF profile.
17
CLKOUT4
O
True Clock Output Channel 4. Default DCLK profile.
18
CLKOUT4
O
Complementary Clock Output Channel 4. Default DCLK profile.
19
VCC3_OUT
P
Power Supply for Clock Group 2 (South)—Channel 4, Channel 5, Channel 6, and Channel 7. See the
Clock Grouping, Skew, and Crosstalk section.
20
CLKOUT6
O
True Clock Output Channel 6. Default DCLK profile.
21
CLKOUT6
O
Complementary Clock Output Channel 6. Default DCLK profile.
22
SCLKOUT7
O
True Clock Output Channel 7. Default SYSREF profile.
23
SCLKOUT7
O
Complementary Clock Output Channel 7. Default SYSREF profile.
24
RSV
R
Reserved Pin. This pin must be tied to ground.
25
CLKIN
I
Complementary Clock Input.
26
CLKIN
I
True Clock Input.
Rev. B | Page 9 of 43