HMC7043 Datasheet, PDF (27/44 Pages) Analog Devices – JEDEC JESD204B support

HMC7043
Data Sheet
Table 18. Supply Network of the HMC7043 by Pin for the Clock Output Network
Per Output Channel
Digital Regulator and Other Sources
Buffer
LVPECL
CML100
High Power
Low Power
LVDS
High Power
Low Power
CMOS
Channel Mux
Different Power Modes Deleted
Digital Delay
Off
Setpoint > 1
Analog Delay
Off
Minimum Setting
Maximum Setting
Divider Logic
0
÷1
÷2
÷3
÷4
÷5
÷6
÷8
÷16
÷32
÷2044
SYNC Logic³
Slip Logic³
Subtotal
Comment
Including term currents
Including term currents
At 307 MHz
At 100 MHz, both sections
Glitchless mode enabled
Not using divider path
Typical Current (mA)
2.5
43
31
24
10
8
25
Included²
2
Included²
3
Included²
9
9
Included²
27
24
31
28
30
26
28
29
29
29
4
4
Profile¹
0 12
3
4
0.5 2.5 2.5
2.5 2.5
43 43
43
10
22
3
0
9
0
2
3
9
0
29
29
2.5 48 87
13 89
1 _{Profile 0 is sleep mode; Profile 1 is fundamental mode; Profile 2 is SYSREF channel matched to fundamental mode; Profile 3 is LVDS—high power signal source from}
other channel; and Profile 4 is worst case configuration for power consumption of a channel.
2 _{The base current consumption of the circuit (for example, mux) is included in the buffer typical current.}
3 _{Currents only occur temporarily during a synchronization event.}
Rev. B | Page 26 of 43