HMC7043 Datasheet, PDF (39/44 Pages) Analog Devices – JEDEC JESD204B support

HMC7043
Data Sheet
SYSREF Status Register (Register 0x0091)
Table 39. SYSREF Status
Address Bits Bit Name
0x0091 [7:5] Reserved
4 Channel outputs
FSM busy
[3:0] SYSREF FSM
State[3:0]
Settings
0000
0010
0100
0101
0110
1010
1011
1100
1101
1110
1111
Description
Reserved.
One of clock outputs FSM requested clock, and it is running.
Indicates the current step of the SYSREF reseed process. Note that the three
different progressions are caused by different trigger events (reseed, pulse
generator, reserved).
Reset.
Done.
Get ready.
Get ready.
Get ready.
Running (pulse generator).
Start.
Power up.
Power up.
Power up.
Clear reset.
Access
R
Bias Settings (Register 0x0096 to Register 0x00B8)
For optimum performance of the chip, Register 0x0098 to Register 0x00B8 must be programmed to a different value than their default value.
Table 40. Reserved Registers
Address Bits Bit Name
0x0098 [7:0] Reserved
0x0099 [7:0] Reserved
0x009D [7:0] Reserved
0x009E [7:0] Reserved
0x009F [7:0] Reserved
0x00A0 [7:0] Reserved
0x00A2 [7:0] Reserved
0x00A3 [7:0] Reserved
0x00A4 [7:0] Reserved
0x00AD [7:0] Reserved
0x00B5 [7:0] Reserved
0x00B6 [7:0] Reserved
0x00B7 [7:0] Reserved
0x00B8 [7:0] Reserved
Settings
Description
Reserved
Reserved
Reserved
Reserved
Clock output driver low power setting (set to 0x4D instead of default value)
Clock output driver high power setting (set to 0xDF instead of default value)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Rev. B | Page 38 of 43