HMC7043 Datasheet, PDF (4/44 Pages) Analog Devices – JEDEC JESD204B support

Data Sheet
HMC7043
SPECIFICATIONS
VCC = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VCC and TA (−40°C to
+85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter¹
SUPPLY VOLTAGE, VCC
VCC1_CLKDIST
VCC2_OUT
VCC3_OUT
VCC4_CLKIN
VCC5_SYSREF
VCC6_OUT
VCC7_OUT
TEMPERATURE
Ambient Temperature Range, TA
Min Typ Max
3.135 3.3 3.465
3.135 3.3 3.465
3.135 3.3 3.465
3.135 3.3
3.135 3.3
3.135 3.3
3.465
3.465
3.465
3.135 3.3 3.465
−40 +25 +85
Unit Test Conditions/Comments
V 3.3 V ± 5%, supply voltage for CLK distribution
V
3.3 V ± 5%, supply voltage for Output Channel 2 and
Output Channel 3
V
3.3 V ± 5%, supply voltage for Output Channel 4, Output
Channel 5, Output Channel 6 and Output Channel 7
V 3.3 V ± 5%, supply voltage for the clock input path
V
3.3 V ± 5%, supply voltage for the common SYSREF divider
V
3.3 V ± 5%, supply voltage for Output Channel 8, Output
Channel 9, Output Channel 10, and Output Channel 11
V
3.3 V ± 5%, supply voltage for Output Channel 0, Output
Channel 1, Output Channel 12, and Output Channel 13
°C
1 _{Maximum values are guaranteed by design and characterization.}
SUPPLY CURRENT
For detailed test conditions, see Table 17 and Table 18.
Table 2
Parameter^{1, 2}
CURRENT CONSUMPTION³
VCC1_CLKDIST
VCC2_OUT⁴
VCC3_OUT⁴
VCC4_CLKIN
VCC5_SYSREF
VCC6_OUT⁴
VCC7_OUT⁴
Total Current
Min Typ Max Unit Test Conditions/Comments
87 125 mA
90 250 mA Typical value is given at TA = 25°C with two LVDS clocks at divide by 8
52 500 mA Typical value is given at 25°C with two LVDS high performance clocks,
fundamental frequency of the clock input (fO), two SYSREF clocks (off )
16 25 mA Typical value is given at TA = 25°C with RF synchronization (RFSYNC) input
buffer off
23 35 mA Typical value is given at TA = 25°C with internal RF SYNC path off
90 500 mA Typical value is given at 25°C with two LVDS high performance clocks at
divide by 2, two SYSREF clocks (off )
100 500 mA Typical value is given at 25°C with two LVDS clocks at divide by 8, two SYSREF
clocks (off )
458
mA
1 _{Maximum values are guaranteed by design and characterization.}
2 _{Currents include LVDS termination currents.}
3 _{Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary}
synchronization events.
4 _{Typical specification applies to a normal usage profile (Profile 1 in Table 17) but very low duty cycle currents (sync events) and some optional features are disabled.}
This specification assumes output configurations as described in the test conditions/comments column.
Rev. B | Page 3 of 43