HMC7043 Datasheet, PDF (16/44 Pages) Analog Devices – JEDEC JESD204B support

Data Sheet
THEORY OF OPERATION
The HMC7043 is a high performance, clock distribution IC
designed for extending the number of clock signals across the
system with minimal noise contribution. The device can be
used for distributing the noise sensitive reference clocks for high
speed data converters with either parallel or serial (JESD204B)
interfaces, FPGAs, and local oscillators. The HMC7043 is
designed to meet the requirements of demanding base station
designs, and offers a wide range of clock management and
distribution features to simplify baseband and radio card clock
tree designs. The device provides 14 low noise and configurable
outputs to offer flexibility in distributing clocks while applying
frequency division, phase adjustment, cycle slip, and external
signal synchronization options.
The HMC7043 generates up to seven DCLK and SYSREF clock
pairs per the JESD204B interface requirements. The system
designer can generate a lower number of DCLK and SYSREF
pairs, and configure the remaining output signal paths as
DCLKs, additional SYSREFs, or other reference clocks with
independent phase and frequency adjustment. Frequency
adjustment can be accomplished by selecting the appropriate
output divider values.
One of the unique features of the HMC7043 is the independent
flexible phase management of each of the 14 channels. Using a
combination of divider slip based, digital (coarse) and analog
(fine) delay adjustments, each channel can be programmed to
have a different phase offset. The phase adjustment capability
allows the designer to offset board flight time delay variations,
match data converter sample windows, and meet JESD204B
synchronization challenges. The output signal path design of
the HMC7043 is implemented to ensure both linear phase
adjustment steps and minimal noise perturbation when phase
adjustment circuits are turned on.
HMC7043
The HMC7043 provides output clock signals of up to 3.2 GHz,
while having the flexibility to support input reference frequencies of
up to 6 GHz when the internal clock division blocks are turned on.
The higher frequency support enables higher bandwidth RF
designs, and allows for distribution of low noise RF phase-locked
loop (PLL) voltage controlled oscillator (VCO) outputs as well
as other critical clocks across the system.
One of the key challenges in JESD204B system design is ensuring
the synchronization of data converter frame alignment across
the system, from the FPGA or digital front end (DFE) to ADCs
and DACs through a large clock tree that may comprise multiple
clock generation and distribution ICs.
There are two input paths on the HMC7043; one is for the clock
signal that is distributed, and the other may be used as an external
synchronization signal. In typical JESD204B systems, serial data
converter interfaces, there may be a need to ensure that all clock
signals that are sent to the data converters have phases which are
controlled by an FPGA. By virtue of the RF SYNC input, the
device ensures that output signals have a deterministic phase
alignment to this synchronization input. The RF SYNC input
can also implement multiple device clock trees by nesting more
than one HMC7043 to generate an even larger clock distribution
network, while still maintaining phase alignment across the
clock tree.
Offering excellent crosstalk, frequency isolation, and spurious
performance, the device generates independent frequencies in
both single-ended and differential formats including LVPECL,
LVDS, CML, and CMOS, and different bias conditions to
offset varying board insertion losses. The outputs can also be
programmed for ac or dc coupling and 50 Ω or 100 Ω internal
and external termination options.
The HMC7043 is programmed via a 3-wire serial port interface
(SPI). The HMC7043 is offered in a 48-lead, 7 mm × 7 mm,
LFCSP package with the exposed pad to ground.
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