HMC7043 Datasheet, PDF (38/44 Pages) Analog Devices – JEDEC JESD204B support

Data Sheet
HMC7043
Alarm Masks Register (Register 0x0071)
Table 36. Alarm Mask Control Register
Address Bits Bit Name
0x0071 [7:5] Reserved
4 Sync request mask
3 Reserved
2 Clock outputs phase status
mask
1 SYSREF sync status mask
0 Reserved
Settings
Description
Reserved
If set, allow sync request signals to generate an alarm signal
Reserved
If set, allow clock output phases status signal to generate an alarm
signal
If set, allow SYSREF sync status signal to generate an alarm signal
Reserved
Access
RW
Product ID Registers (Register 0x0078 to 0x007A)
Table 37. Product ID Registers
Address
Bits
Bit Name
0x0078
[7:0]
Product ID Value[7:0] (LSB)
0x0079
[7:0]
Product ID Value[15:8] (Mid)
0x007A
[7:0]
Product ID Value[23:16] (MSB)
Settings
Description
24-bit product ID value low
24-bit product ID value mid
24-bit product ID value high
Access
R
R
R
Alarm Readback Status Registers (Register 0x007B to 0x007F)
Table 38. Alarm Readback Status Registers
Address Bits Bit Name
Settings
0x007B [7:1] Reserved
0 Alarm signal
0x007D [7:5] Reserved
4 Sync request status
3 Reserved
2 Clock outputs phases
status
0
1
1 SYSREF sync status
0
1
0 Reserved
1
0x007F [7:0] Reserved
Description
Reserved.
Readback alarm status from SPI.
Reserved.
Unsynchronized.
Reserved.
SYSREF alarm.
SYSREF of the HMC7043 is not valid; that is, the phase output is not stable.
SYSREF of the HMC7043 is valid; that is, the phase output is stable.
SYSREF SYNC status alarm.
The HMC7043 has been synchronized with an external sync pulse or a
sync request from the SPI.
The HMC7043 never synchronized with an external sync pulse or a sync
request from the SPI.
Reserved.
Reserved.
Access
R
R
R
Rev. B | Page 37 of 43