HMC7043 Datasheet, PDF (40/44 Pages) Analog Devices – JEDEC JESD204B support

Data Sheet
HMC7043
Clock Distribution (Register 0x00C8 to Register 0x0152)
The bit descriptions in Table 41 apply to all 14 channels.
Table 41. Channel 0 to Channel 13 Control
Address
Bits Bit Name
0x00C8, 0x00D2, 0x00DC, 7
0x00E6, 0x00F0, 0x00FA,
0x0104, 0x010E, 0x0118,
0x0122, 0x012C, 0x0136,
6
0x0140, 0x014A
High performance
mode
SYNC enable
5
Slip enable
4
Reserved
[3:2] Start-Up
Mode[1:0]
1
Multislip enable
0x00C9, 0x00D3, 0x00DD,
0x00E7, 0x00F1, 0x00FB,
0x0105, 0x010F, 0x0119,
0x0123, 0x012D, 0x0137,
0x0141, 0x014B
0x00CA, 0x00D4, 0x00DE,
0x00E8, 0x00F2, 0x00FC,
0x0106, 0x0110, 0x011A,
0x0124, 0x012E, 0x0138,
0x0142, 0x014C
0x00CB, 0x00D5, 0x00DF,
0x00E9, 0x00F3, 0x00FD,
0x0107, 0x0111, 0x011B,
0x0125, 0x012F, 0x0139,
0x0143, 0x014D
0x00CC, 0x00D6, 0x00E0,
0x00EA, 0x00F4, 0x00FE,
0x0108, 0x0112, 0x011C,
0x0126, 0x0130, 0x013A,
0x0144, 0x014E
0x00CD, 0x00D7, 0x00E1,
0x00EB, 0x00F5, 0x00FF,
0x0109, 0x0113, 0x011D,
0x0127, 0x0131, 0x013B,
0x0145, 0x014F
0
Channel enable
[7:0] 12-Bit Channel
Divider[7:0] (LSB)
[7:4] Reserved
[3:0] 12-Bit Channel
Divider[11:8]
(MSB)
[7:5] Reserved
[4:0] Fine Analog
Delay[4:0]
[7:5] Reserved
[4:0] Coarse Digital
Delay[4:0]
[7:0] 12-Bit Multislip
Digital Delay[7:0]
(LSB)
Settings¹
00
01
10
11
0
1
Description
High performance mode. Adjusts the divider and buffer
bias to improve swing/phase noise at the expense of
power.
Susceptible to SYNC event. The channel can process a
SYNC event to reset the phase.
Susceptible to slip event. The channel can process a slip
request from SPI or GPI. Note that if slip enable is true,
but multislip is off, a channel slips by 1 clock input cycle
on an explicit slip request broadcast from the SPI/GPI.
Reserved.
Configures the channel to normal mode with
asynchronous startup, or to a pulse generator mode with
dynamic start-up. Note that this must be set to
asynchronous mode if the channel is unused.
Asynchronous.
Reserved.
Reserved.
Dynamic.
Allow multislip operation (default = 0 for SYSREF, 1 for
DCLK).
Do not engage automatic multislip on channel startup.
Multislip events after SYNC or pulse generator request, if
the slip enable bit = 1.
Channel enable. If this bit is 0, channel is disabled.
12-bit channel divider setpoint LSB. The divider supports
even divide ratios from 2 to 4094. The supported odd
divide ratios are 1, 3, and 5. All even and odd divide ratios
have 50.0% duty cycle.
Reserved.
12-bit channel divider setpoint MSB.
Reserved.
24 fine delay steps. Step size = 25 ps. Values bigger than
23 has no effect on analog delay.
Reserved.
17 coarse delay steps. Step size = ½ input clock cycle. This
flip flop (FF)-based digital delay does not increase noise
level at the expense of power. Values bigger than 17 have
no effect on coarse delay.
12-bit multislip digital delay amount LSB. Step size =
(delay amount: MSB + LSB) × input clock cycles. If
multislip enable bit = 1, any slip events (caused by GPI,
SPI, SYNC, or pulse generator events) repeat the number
of times set by 12-Bit Multislip Digital Delay[11:0] to
adjust the phase by step size.
Access
RW
RW
RW
RW
RW
RW
Rev. B | Page 39 of 43