HMC7043 Datasheet, PDF (19/44 Pages) Analog Devices – JEDEC JESD204B support

HMC7043
Each of the 14 output channels are logically identical. The only
distinction between the SYSREF and DCLK channels is in the
SPI configuration, and in how they are used. Each channel
contains independent dividers, phase adjustment, and analog
delay circuits. This combination provides the ultimate flexibility,
cleanly accommodating nonJESD204B devices in the system.
In addition to the 14 output channel dividers, an internal SYSREF
timer continually operates, and the synchronization of the output
channel dividers occurs deterministically with respect to this
timer, which the user can rephased deterministically by the user
through GPI or SPI or deterministically by using the RFSYNCIN/
RFSYNCIN differential pins.
The pulse generator functionality of the JESD204B standard
involves temporarily generating SYSREF output pulses, with
appropriate phasing, to downstream devices. The centralized
SYSREF timer and the associated SYNC/pulse generator control
manage the process of enabling the intended SYSREF channels,
phasing them, and then disabling them for signal integrity and
power saving advantages.
Basic Output Divider Channel
Each of the 14 output channels are logically identical, and support
divide ratios from 1 to 4094. The supported odd divide ratios
(1, 3, or 5) have 50.0% duty cycle. The only distinction between
a SYSREF channel and a device clock channel is in the SPI
configuration and the typical usage of a given channel.
For basic functionality and phase control, each output path
consists of the following:
• Divider—generates the logic signal of the appropriate
frequency and phase
• Digital phase adjust—adjusts the phase of each channel in
increments of ½ clock input cycles
• Retimer—a low noise flip flop to retime the channel,
removing any accumulated jitter
• Analog fine delay—provides a number of ~25 ps delay steps
• Selection mux—selects the fundamental, divider, analog
delay, or an alternate path
• Multimode output buffer—low noise LVDS, CML, CMOS,
or LVPECL
The digital phase adjuster and retimer launch on either clock
phase of the clock input, depending on the digital phase adjust
setpoint (Coarse Digital Delay[4:0]).
Data Sheet
To support divider synchronization, arbitrary phase slips, and
pulse generator modes, the following blocks are included:
• A clock gating stage pauses the clock for synchronization
or slip operations
• An output channel leaf (×14) controller that manages slip,
synchronization, and pulse generators with information
from the SYSREF finite state machine (FSM)
Each channel has an array of control signals. Some of the
controls are described in Table 10.
System wide broadcast signals can be triggered from the SPI or
general-purpose input (GPI) port to issue a SYNC command
(to align dividers to the system internal SYSREF timer), issue a
pulse generator stream, (temporarily exporting SYSREF signals to
receivers), or to cause the dividers to slip a number of clock
input cycles to adjust their phases.
Individual dividers can be made sensitive to these events by
adjusting their slip enable, SYNC enable, and Start-Up Mode[1:0]
configuration, as described in Table 11.
When output buffers are configured in CMOS mode and phase
alignment is required among the outputs, additional multislip
delays must be issued for Channel 0, Channel 3, Channel 5,
Channel 6, Channel 9, Channel 10, and Channel 13. The value
of the delay must be as large as half of the selected divider ratio.
Note that this requirement of having additional multislip delays
is not needed when the channels are used in LVPECL, CML, or
LVDS mode.
If a channel is configured to behave as a pulse generator, to
temporarily power up and power down according to the GPI
and SPI pulse generator commands; additional controls define the
behavior outside of the pulse generator chain (see Table 12).
Each divider has an additional phase offset register that adjusts
the start phase or influences the behavior of slip events sent via
the SPI (see Table 13).
Table 14 outlines the typical configuration combinations for a
DCLK channel relative to a SYSREF synchronization channel.
Note that other combinations are possible. Synchronization of
downstream devices can be managed manually, or by using the
pulse generator functionality of the HMC7043. See the Typical
Programming Sequence section for more information about the
differences between the two methods.
Rev. B | Page 18 of 43