HMC7043 Datasheet, PDF (34/44 Pages) Analog Devices – JEDEC JESD204B support

Data Sheet
HMC7043
CONTROL REGISTER MAP BIT DESCRIPTIONS
Global Control (Register 0x0000 to Register 0x0009)
Table 21. Global Soft Reset Control
Address Bits Bit Name Settings
0x0000 [7:1] Reserved
0 Soft reset
Description
Reserved
Resets all registers, dividers, and FSMs to default values
Access
RW
Table 22. Global Request and Mode Control
Address Bits Bit Name
Settings
0x0001 7
Reseed request
6
High performance
distribution path
0
1
5
Reserved
4
Reserved
3
Mute output drivers
2
Pulse generator request
1
Restart dividers/FSMs
0
Sleep mode
0x0002 [7:2] Reserved
1
Multislip request
0
Reserved
Description
Requests the centralized resync timer and FSM to reseed any of the output
dividers that are programmed to pay attention to sync events. This signal is
rising edge sensitive, and is only acknowledged if the resync FSM has
completed all events (has finished any previous pulse generator and/or
sync events, and is in the done state (SYSREF FSM State[3:0] = 0010).
High performance distribution path select. The clock distribution path
has two modes.
Power priority.
Noise priority. Provides the option for better noise floors on the divided
output signals.
Reserved.
Reserved.
Mutes the output drivers (dividers still run in the background).
Asks for a pulse stream (see the Typical Programming Sequence section).
Resets all dividers and FSMs. Does not affect configuration registers.
Forces shutdown. Output network, and I/O buffers are disabled.
Reserved.
Requests a slip or multislip event from all divider channels that are
sensitive to slip or multislip commands. The dividers are rising edge
sensitive and take some time to process the request, after which the
phase synchronization alarm is asserted.
Reserved.
Access
RW
RW
Table 23. Global Enable Control
Address Bits Bit Name
0x0003 [7:6] Reserved
5
RF reseeder enable
[4:3] Reserved
2
SYSREF timer enable
1
Reserved
0
Reserved
0x0004 7
Reserved
[6:0] Seven Pairs of 14-Channel Outputs Enable[6:0]
Settings
[0]
[1]
[2]
[3]
[4]
[5]
[6]
Description
Reserved
Enable RF reseed for SYSREF
Reserved
Enable internal SYSREF time reference
Reserved
Reserved
Reserved
Enable Channel 0 and 1
Enable Channel 2 and 3
Enable Channel 4 and 5
Enable Channel 6 and 7
Enable Channel 8 and 9
Enable Channel 10 and 11
Enable Channel 12 and 13
Access
RW
RW
Table 24. Global Mode and Enable Control
Address Bits Bit Name
Settings
0x0005 [7:0] Reserved
Description
Reserved
Rev. B | Page 33 of 43
Access
RW