HMC7043 Datasheet, PDF (37/44 Pages) Analog Devices – JEDEC JESD204B support

HMC7043
Data Sheet
SYSREF/SYNC (Register 0x005A to Register 0x005D)
Table 31. Pulse Generator Control
Address Bits Bit Name
0x005A [7:3] Reserved
[2:0] Pulse Generator
Mode
Selection[2:0]
Settings
000
001
010
011
100
101
110
111
Description
Reserved.
SYSREF output enable with pulse generator.
Level sensitive. When the GPI is configured to issue a pulse generator
request (GPI Selection[2:0] = 100), or a pulse generator request is issued
through the SPI or as a SYNC pin-based pulse generator, run the pulse
generator. Otherwise, stop the pulse generator.
1 pulse.
2 pulses.
4 pulses.
8 pulses.
16 pulses.
16 pulses.
Continuous mode (50% duty cycle).
Access
RW
Table 32. SYNC Control
Address Bits Bit Name
0x005B [7:3] Reserved
2
SYNC retime
1
Reserved
0
SYNC polarity
Settings Description
Reserved
0
Bypass the retime (non-deterministic SYNC event condition)
1
Retime the external SYNC (deterministic SYNC event condition)
Reserved
SYNC polarity (must be 0 if not using CLKIN/CLKIN as the input)
0
Positive
1
Negative
Access
RW
Table 33. SYSREF Timer Control
Address Bits Bit Name
0x005C [7:0] SYSREF Timer[7:0]
(LSB)
0x005D
[7:4] Reserved
[3:0] SYSREF Timer[11:8]
(MSB)
Settings
Description
12-bit SYSREF timer setpoint LSB. This sets the internal beat frequency of
the master timer, which controls synchronization and pulse generator
events. Set the 12-bit timer to a submultiple of the lowest output SYSREF
frequency, and program it to be no faster than 4 MHz.
Reserved.
12-bit SYSREF timer setpoint MSB.
Access
RW
RW
Clock Distribution Network (Register 0x0064 to Register 0x0065)
Table 34. Clock Input Control
Address Bits Bit Name
0x0064 [7:2] Reserved
1
Divide by 2 on clock input
0
Low frequency clock input
Settings
Description
Reserved
Use divide by 2 on clock input path
Changes bias to Class A for low frequency clock input
Access
RW
Table 35. Analog Delay Common Control
Address Bits Bit Name
Settings
0x0065 [7:1] Reserved
0 Analog delay low
power mode
Description
Reserved.
Analog delay is low power mode. Can save power for low settings of analog
delay, but is not glitchless between setpoints.
Access
RW
Rev. B | Page 36 of 43