HMC7043 Datasheet, PDF (13/44 Pages) Analog Devices – JEDEC JESD204B support

HMC7043
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0 1 2 3 4 5 6 7 8 9 10
TIME (ns)
Figure 9. Differential CLKOUT0/CLKOUT0 Voltage at 614.4 MHz, LVPECL
0.6
CLKOUT0
2.5
CLKOUT2
VALID PHASE ALARM
0.4
2.0
0.2
1.5
0
1.0
–0.2
0.5
–0.4
0
–0.6
0
–0.5
200
400
600
800
1000
TIME (ns)
Figure 10. Output Channel Synchronization Before and After Rephase
0.6
2.5
CLKOUT0
CLKOUT2
VALID PHASE ALARM
0.4
2.0
0.2
1.5
0
1.0
–0.2
0.5
–0.4
0
–0.6
330
335
340
345
TIME (ns)
–0.5
350
Figure 11. Output Channel Synchronization Before Rephase
Data Sheet
0.6
2.5
0.4
2.0
0.2
1.5
0
1.0
–0.2
0.5
–0.4
–0.6
695
CLKOUT0 VALID PHASE ALARM
CLKOUT2
700
705
710
TIME (ns)
0
–0.5
715
Figure 12. Output Channel Synchronization After Rephase
30
25
20
15
–40°C
+25°C
+85°C
10
DELAY STEP
Figure 13. Analog Delay Step Size vs. Delay Step over Temperature,
LVPECL at 983.04 MHz
800
700
600
500
400
300
200
100
0
–100
–200
–40°C
+27°C
+85°C
FUND:FUNDAMENTAL MODE AT 2949.12MHz
DIS: ANALOG DELAY IS DISABLED AT 983.04MHz
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
DELAY STEP
Figure 14. Analog Delay vs. Delay Setting over Temperature, LVPECL at
983.04 MHz
Rev. B | Page 12 of 43