HMC7043 Datasheet, PDF (18/44 Pages) Analog Devices – JEDEC JESD204B support

Data Sheet
Single-Ended Operation
The buffers can support a single-ended signal with slightly reduced
input sensitivity and bandwidth. If driving any of the buffers
single-ended, ac couple the unused leg of the buffer to ground
at the input of the die.
Maximum Signal Swing Considerations
The internal supplies to these input buffers are supplied directly
from 3.3 V. The ESD network and parasitic diodes can generally
shunt away excess power and protect the internal circuits
(withstanding reference powers above 13 dBm). Nevertheless,
to protect from latch-up concerns, the signals on the reference
inputs must not exceed the 3.3 V internal supply. For a 2.1 V
common mode, 50 Ω single-ended source, this allows ~1200 mV
of amplitude, or 11 dBm maximum reference power.
CLOCK OUTPUT NETWORK
The HMC7043 is a high performance clock buffer, is appropriate
for JESD204B data converters, and much of the uniqueness of a
JESD204B clock generation chip relates to the array of output
channels. In this device, the output network requirements include
• A large number of device clock (DCLK) and synchronization
(SYSREF) channels
• Very good phase noise floor of the DCLK channels that can
be connected to critical data converter sample clock inputs
• Deterministic phase alignment between all output channels
relative to one another
SYSREF INPUT NETWORK
HMC7043
• Fine phase control of synchronization channels with
respect to the DCLK channel
• Frequency coverage to satisfy typical clock rates in systems
• Skew between SYSREF and DCLK channels that is much
less than a DCLK period
• Spur and crosstalk performance that does not impact
system budgets
The HMC7043 output network supports the following recom-
mended features, which are sometimes critical in user applications:
• Deterministic synchronization of the output channels with
respect to an external signal (RFSYNC), which allows
multichip synchronization and clean expansion to larger
systems
• Pulse generator behavior to temporarily generate a
synchronization pulse stream at a user request
• The flexibility to define unused JESD204B SYSREF and
DCLK channels for other purposes
• Glitchless phase control of signals relative to each other
• 50% duty cycle clocks with odd division ratios
• Multimode output buffers with a variety of swings and
termination options
• Skew between all channels is much less than a DCLK period
• Adjustable performance vs. power consumption for less
sensitive clock channels
RF
SYNC
DQ
CLKIN PATH
RESET
SYSREF TIMER
SYNC/PULSE GENERATOR
CONTROL
PULSE GENERATOR REQUEST (FROM SPI OR GPI PIN)
SYNC REQUEST (FROM SPI OR GPI PIN)
SYNC_FSM_STATE OUTPUT CHANNEL ×14
LEAF CONTROLLER
CLOCK
GATING
DIVIDER
DIGITAL
DELAY AND
RETIME
Figure 25. Clock Output Network Simplified Diagram
Rev. B | Page 17 of 43