HMC7043 Datasheet, PDF (25/44 Pages) Analog Devices – JEDEC JESD204B support

HMC7043
7. Issue a software restart to reset the system and initiate
calibration. Toggle the restart dividers/FSMs bit to 1 and
then back to 0.
8. Send a sync request via the SPI (set the reseed request bit)
to align the divider phases and send any initial pulse
generator stream.
9. Wait six SYSREF periods (6 × SYSREF Timer[11:0]) to
allow the outputs to phase appropriately (~3 μs in typical
configurations).
10. Confirm that the outputs have all reached their phases by
checking that the clock outputs phases status bit = 1.
11. At this time, initialize any other devices in the system.
Configure the slave JESD204B devices in the system to
operate with the SYSREF signal outputs from the HMC7043.
The SYSREF channels from the HMC7043 can be on either
asynchronously or dynamically, and may temporarily turn
on for a pulse generator stream.
12. Slave JESD204B devices in the system must be configured
to monitor the input SYSREF signal exported from the
HMC7043. At this point, SYSREF channels from the
HMC7043 can either be on asynchronously (running) or on
dynamically (temporarily turn on for a pulse generator train).
13. When all JESD204B slaves are powered and ready, send a
pulse generator request to send out a pulse generator chain on
any SYSREF channels programmed for pulse generator mode.
The system is initialized.
For power savings and the reduction of the cross coupling of
frequencies on the HMC7043, shut down the SYSREF channels.
1. Program each JESD204B slave to ignore the SYSREF input
channel.
2. On the HMC7043, disable the individual channel enable bits
of each SYSREF channel.
Data Sheet
To resynchronize one or more of the JESD204B slaves, use the
following procedure:
1. Set the channel enable and SYNC enable bit of the SYSREF
channel of interest.
2. To prevent an output channel from responding to a sync
request, disable the SYNC enable mask of each channel so
that it continues to run normally without a phase adjustment.
3. Issue a reseed request to phase the SYSREF channel
properly with respect to the DCLK.
4. Enable the JESD204B slave sensitivity to the SYSREF channel.
5. If the SYSREF channel is in pulse generator mode, wait at
least 20 SYSREF periods from Step 3, and issue a pulse
generator request.
POWER SUPPLY CONSIDERATIONS
The output buffers are susceptible to supply with a certain
extent. The output buffers are also susceptible to supply noise,
but to a lesser extent. A noise tone of −60 dBV at a 40 MHz
offset results in a −90 dBc tone at the output of the buffers in
CML mode and −85 dBc in LVPECL mode. This result is a
relatively flat frequency response, and these numbers are
measured differentially. Phase noise/spurs caused by supply
noise on the output buffers do not scale with output frequency.
Table 17 lists the supply network of the HMC7043 by pin, showing
the relevant functional blocks. Three different usage profiles are
defined for the network, not including the output channel
supplies, which are accounted for separately.
The values listed under Profile 0 to Profile 2 in Table 17 and
Table 18 are the typical currents of that block or feature. If a
number is not listed in a profile column, a typical profile does
not exist for that block or feature, but the user can mix and
match features outside of the profile list, and can determine
what the power consumption is going to be given the current
listings per feature.
Rev. B | Page 24 of 43