HMC7043 Datasheet, PDF (5/44 Pages) Analog Devices – JEDEC JESD204B support

HMC7043
Data Sheet
DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS
Table 3.
Parameter
Min
DIGITAL INPUT SIGNALS (RESET, SLEN, SCLK)
Safe Input Voltage Range
−0.1
Input Load
Input Voltage
Input Logic High
1.2
Input Logic Low
0
SPI Bus Frequency
DIGITAL BIDIRECTIONAL SIGNALS
CONFIGURED AS INPUTS (SDATA, GPIO)
Safe Input Voltage Range
−0.1
Input Capacitance
Input Resistance
Input Voltage
Input Logic High
1.22
Input Logic Low
0
Input Hysteresis
GPIO ALARM MUXING/DELAY
Delay from Internal Alarm/Signal to
General-Purpose Output (GPO) Driver
DIGITAL BIDIRECTIONAL SIGNALS
CONFIFURED AS OUTPUTS (SDATA, GPIO)
CMOS Mode
Logic 1 Level
1.6
Logic 0 Level
Output Drive Resistance (RDRIVE)
Output Driver Delay (tDGPO)
Typ
Max
+3.6
0.3
VCC
0.5
10
+3.6
0.4
50
VCC
0.24
0.2
2
1.9
2.2
0
0.1
50
1.5 + 42 × CLOAD
Maximum Supported DC Current¹
0.6
Open-Drain Mode
Logic 1 Level
3.6
Logic 0 Level
Pull-Down Impedance
Maximum Supported Sink Current¹
0.13
0.28
60
5
1 _{Guaranteed by design and characterization for long-term reliability.}
Unit Test Conditions/Comments
V
pF
V
V
MHz
V
pF
GΩ
V
V
V
Occurs around 0.85 V
ns Does not include tDGPO
V
V
Ω
ns Approximately 1.5 ns + 0.69 × RDRIVE × CLOAD
(CLOAD in nF)
mA
External 1 kΩ pull-up resistor
V
3.6 V maximum permitted; specifications set by
external supply
V
Against a 1 kΩ external pull-up resistor to 3.3 V
Ω
mA
CLOCK INPUT PATH SPECIFICATIONS
Table 4.
Parameter
Min Typ Max Unit Test Conditions/Comments
CLK INPUT (CLKIN) CHARACTERISTICS
Recommended Input Power, AC-Coupled
Differential
−6
+8 dBm
Single-Ended¹
−10
+6 dBm Noise floor degrade by 3 dB at fCLKIN = 2400 MHz
Return Loss
−12
dB When terminated with 100 Ω differential
Clock Input Frequency (fCLKIN)
200
3200 MHz Fundamental mode; if <1 GHz, set the low frequency
clock input path enable bit (Register 0x0064, Bit 0)
200
6000 MHz Using clock input ÷ 2
Common-Mode Range
0.4
2.4 V
1 _{Guaranteed by design and characterization.}
Rev. B | Page 4 of 43