Z8523L08VEG Datasheet, PDF (92/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
87
Table 46 lists the Z80230 system timing parameter details.
Table 46. Z80230 System Timing Table
10 MHz
No. Symbol
Parameter
Min. Max.
1
TdRXC (REQ) RxC High to W/REQ Valid
13
17
2
TdRXC (W) RxC High to Wait Inactive
13
19
3
TdRXC (SY) RxC High to SYNC Valid
9
12
4
TdRXC (INT), RxC High to INT Valid
Z80230
13
17
2
3
5
TdTXC (REQ) TxC Low to W/REQ Valid
11
14
6
TdTXC (W) TxC Low to Wait Inactive
8
14
7
TdTXC (DRQ) TxC Low to DTR/REQ Valid
8
TdTXC (INT), TxC Low to INT Valid
Z80230
7
9
2
3
9
TdSY (INT) SYNC to INT Valid
2
6
+2
+3
10 TdEXT (INT), DCD or CTS to INT Valid
2
3
Z80230
Notes:
1. Open-drain output, measured with open-drain test load.
2. RxC is RTxC or TRxC, whichever is supplying the receive clock.
3. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
4. Units equal to AS.
5. Units equal to TcPc.
16 MHz
Min.
13
13
9
13
2
11
8
Max.
17
19
12
17
3
14
14
7
9
2
3
2
6
+2
+3
3
8
Notes
2, 5
1, 2, 5
2, 5
1, 2, 4
3, 5
1, 3, 5
3, 5
1, 3, 4
1, 5
1, 4
Z85230/L AC Characteristics
Figure 29 on page 88 displays the Z85230/L Read and Write Timing Diagram. Figure 30
on page 89 displays the Z85230/L Reset Timing Diagram. Figure 31 on page 89 displays
the Z85230/L Interrupt Acknowledge Timing Diagram. Figure 32 on page 89 displays the
Z85230/L Cycle Timing Diagram.
PS005308-0609
Electrical Characteristics