Z8523L08VEG Datasheet, PDF(109/118 Page) Zilog, Inc. – Enhanced Serial Communications Controller

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Z8523L08VEG Datasheet, PDF (109/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

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Z80230/Z85230/L

Product Specification

104

Default RR10 Value Problem Description

RR10 bit 6, the 2 clock missing bit, is sometimes erroneously set to indicate that the DPLL

detects a clock edge in two successive tries after hardware reset.

Default RR10 Value Problem Solution

Ignore the first bit 7 value Read from RR10 after reset.

CRC Problem Description

The CRC cannot be interpreted from the Receive FIFO when one or two residue bits are

sent. The CRC value is received and checked correctly but is not loaded to the Receive

FIFO. The two types of CRC problems are described below:

â¢ Two Residue bits (Residue code is 000)

The last three bytes of the Receive FIFO read:

C15 C14 C13 C12 C11 C10 C9

Bits 6 and 7 of the CRC are lost.

â¢ One Residue Bit (Residue code is 111)

The last three bytes of the Receive FIFO read:

C15 C14 C13 C12 C11 C10 C9

Bit 7 of the CRC is lost.

The CRC is received and loaded into the Receive FIFO in other situations (that is, the 0, 3,

4, 5, 6, and 7 residue bits).

The Residue code, RR1 bits 3, 2, and 1, is reported independently of the number of residue

bits sent.

CRC Problem Solution

Ignore the CRC value read from the Receive FIFO if one or two residue bits are sent.

PS005308-0609

Z80230/Z85230/L Errata

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