Z8523L08VEG Datasheet, PDF (108/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
103
back frames are sent. The TxD output is automatically forced High for eight bit-times and
the first byte of the second frame is corrupted. In a multiple-frame transmission, a zero (0)
bit is inserted before the opening flag of the second frame.
Automatic TxD Forced High Problem Solutions
Send back-to-back frames in FLAG IDLE mode, because the Automatic TxD Forced High
feature creates problems only if all the following conditions are true:
• Back-to-back frame transmission
• NRZI
• Mark Idle
Setting the system in Flag Idle mode (WR10 bit 3 equals 0) in frame transmission allows
back-to-back frames to be sent without any data corruption.
SDLC FIFO Overflow Problem Description
In SDLC mode, bit 7 of RR7 (FIFO Overflow status bit) is set if an 11th frame ends while
the FIFO is full (that is, ten frames have accumulated in the Status FIFO and have not yet
been read by the processor). Under this circumstance, the status FIFO is locked and no
data can be written to the Status FIFO until bit 7 of RR7 is reset.
If the ESCC is set up in ANTI-LOCK mode (that is, the SDKC FIFO is used when
Receive Interrupts on Special Condition Only is enabled), the only method of resetting bit
7 of RR7(the FIFO Overflow bit) is to reset and set WR15 bit 2 (SDLC FIFO Enable Bit).
This action causes the SDLC FIFO to reset and all the SDLC frame information is lost.
With no Anti-Lock feature, the FIFO Overflow status bit is reset if the SDLC FIFO is
read.
If the ESCC is in NRZI and Mark Idle in back-to-back frame transmission, (one the FIFO
Overflow bit RR7 bit 7) is set, the only method of resetting the status is to reset and set
WR15 bit 2. This action causes the SDLC FIFO to reset and the unprocessed frame infor-
mation stored in the SDLC FIFO is lost.
SDLC FIFO Overflow Problem Solution
Do not use Receive Interrupts on Special Conditions Only and Mark Idle if there is a pos-
sibility of Status FIFO Overflow.
Default RR0 Value Problem Description
RR7 bit 7, the Break/Abort status bit, does not always clear after reset.
Default RR0 Value Problem Solution
Ignore the first bit 7 value read from RR0 after reset.
PS005308-0609
Z80230/Z85230/L Errata