Z8523L08VEG Datasheet, PDF (20/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
15
CPU/DMA BLOCK TRANSFER
The ESCC provides a BLOCK TRANSFER mode to accommodate CPU/DMA controller.
The BLOCK TRANSFER mode uses the WAIT/REQUEST output in conjunction with the
WAIT/REQUEST bits in WR1. The WAIT/REQUEST output can be defined as a WAIT
line in the CPU BLOCK TRANSFER mode or as a REQUEST line in the DMA BLOCK
TRANSFER mode.
To a DMA controller, the ESCC REQUEST output indicates that the ESCC is ready to
transfer data to or from memory.
To the CPU, the WAIT line indicates that the ESCC is not ready to transfer data, thereby
requesting the CPU to extend the I/O cycle.
The DTR/REQUEST line allows full-duplex operation under DMA control. The ESCC
can be programmed to deassert the DTR/REQUEST pin with the same timing as the
WAIT/REQUEST pin if WR7’ bit 4 is 1.
ESCC Data Communications Capabilities
The ESCC provides two independent full-duplex programmable channels for use in any
common ASYNCHRONOUS or SYNCHRONOUS data communication protocols (see
Figure 8). The channels have identical features and capabilities.
Start
Parity
Stop
Marking Line
Data
Data
Asynchronous
Data
Marking Line
SYNC Data
Monosync
Data CRC1 CRC2
SYNC
SYNC Data
Signal
Bisync
Data
CRC1 CRC2
Data
Data CRC1 CRC2
External Sync
Flag Address Control
Information CRC1 CRC2 Flag
SDLC/HDLC/X.25
Figure 8. Various ESCC Protocols
PS005308-0609
Functional Description