Z8523L08VEG Datasheet, PDF (32/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
27
synchronous frame is guaranteed to generate two TBE interrupts even if a Reset Transmit
Buffer Interrupt command for the data created interrupt is issued after the CRC interrupt
occurs (Time A in Figure 13). Two Reset TBE commands are required. The TxIP latches
if the EOM latch resets before the end of the frame.
Data
Data
CRC1
CRC2
Flag
TxBE
TxIP Bit
TxIP 1
Figure 13. TxIP Latching
Time A
TxIP 2
DPLL Counter Tx Clock Source
When the DPLL is selected as the transmit clock source, the DPLL counter output is the
DPLL source clock divided by the appropriate divisor for the programmed data encoding
format. In FM mode (FM0 or FM1), the DPLL counter output signal is the input frequency
divided by 16.
In NRZI mode, the DPLL counter output signal is the input clock cycle divided by 32.
This feature provides a jitter-free output signal that replaces the DPLL transmit clock out-
put as the transmit clock source. This action has no effect on the use of the DPLL as the
receive clock source (see Figure 14).
DPLL CLK
Input
DPLL
DPLL Output to Receiver
DPLL Counter
DPLL Output to Transmitter
Input Frequency Divided by 16 (FM0 or FM1)
Input Clock Cycle Divided by 32 for NRZI
Figure 14. DPLL Outputs
Read Register 0 Status Latched During Read Cycle
The contents of Read Register 0, RR0 is latched during a Read operation. The ESCC pre-
vents the contents of RR0 from changing during a Read operation. But, the SCC allows
the status of RR0 to change while reading the register and may require reading RR0 twice.
The contents of RR0 is updated after the rising edge of RD signal.
PS005308-0609
Z80230/Z85230/L Enhancements