Z8523L08VEG Datasheet, PDF(30/118 Page) Zilog, Inc. – Enhanced Serial Communications Controller

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Z8523L08VEG Datasheet, PDF (30/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

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Z80230/Z85230/L

Product Specification

D7âD0

DTR/REQ

Transmit Data

WR7 bit 4 =1

WR7 bit 4 = 0

WAIT/REQ

Figure 12. DMA Request on Transmit Deactivation Timing

Bit 3 (Receive FIFO Interrupt Level)

This bit sets the interrupt level of the receive FIFO. If this bit is set to 1, the receive data

available bit is asserted when the receive FIFO is half full (4 bytes available). If this bit is

reset to 0, the Receive Data Available interrupt is requested when all bytes are set. For

more information, see 8-Byte Receive FIFO on page 22.

Bit 2 (Automatic RTS Pin Deassertion)

This bit controls the timing of the deassertion of the RTS pin in SDLC mode. If this bit is

1 and WR5 bit 1 is set to 0 during the transmission of an SDLC frame, the deassertion of

the RTS pin is delayed until the last bit of the closing flag clears the TxD pin. The RTS pin

is pulled High after the rising edge of the transmit clock cycle from the last bit of the clos-

ing flag. This action implies that the ESCC must be programmed for Flag on Underrun

(WR10 bit 2 is 0) for the RTS pin to deassert at the end of the frame. This feature works

independently of the programmed Transmitter Idle state. In SYNCHRONOUS mode other

than SDLC, the RTS pin immediately follows the state programmed into WR5 bit 1. When

WR7â bit 2 is set to 0, the RTS follows the state of WR5 bit 1.

Bit 1 (Automatic EOM Reset)

If this bit is 1, the ESCC automatically resets the Tx Underrun/EOM latch and presets the

transmit CRC generator to its programmed preset state (per values set in WR5 bit 2 and

WR10 bit 7). Therefore, it is not necessary to issue the Reset Tx Underrun/EOM Latch

command when this feature is enabled.

Bit 0 (Automatic Tx SDLC Flag)

If this bit is 1, the ESCC automatically transmits an SDLC flag before transmitting data.

This action removes the requirement to reset the Mark Idle bit (WR10 bit 3) before writing

data to the transmitter.

PS005308-0609

Z80230/Z85230/L Enhancements

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