Z8523L08VEG Datasheet, PDF (115/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
108
Index
A
abort character 18
absolute maximum ratings 75
AC characteristics 78
AC characteristics table, Z85230 90
AC characteristics, Z85230 87
asynchronous receive mode 4
auto echo and logical loopback 21
auto enable 4
automatic EOM reset 28
B
baud rate generator 19
bisync 4, 16
block transfer, CPU/DMA 15
C
capacitance 76
character
abort 18
EOP 18
code
NRZ 18
NRZI 18
command
reset highest IUS 28
reset Tx CRC generator 28
reset Tx/underrun latch 28
counter
transmit clock 5
CRC problem
description 104
solution 104
CRC reception in SDLC mode 26
Customer Feedback Form 112
PS005308-0609
D
data communications capabilities 15
data encoding 20
DC characteristics 77
default RR0 value problem
description 103
solution 103
default RR10 value problem
description 104
solution 104
device type identification 24
diagram
40-pin DIP package 105
44-pin PLCC package 106
automatic RTS deactivation 102
cycle timing, Z85230 89
data encoding methods 20
detecting 5-or 7-bit characters 16
DPLL Outputs 27
ESCC protocols 15
general timing, Z80230 81
general timing, Z85230 94
interrupt acknowledge cycle timing, Z80230
72
interrupt acknowledge cycle timing, Z85230
74
interrupt acknowledge timing, Z80230 80
interrupt acknowledge timing, Z85230 89
interrupt priority schedule 13
read cycle timing, Z80230 71
read cycle timing, Z85230 73
read/write timing, Z80230 79
read/write timing, Z85230 88
receive data path 9
reset timing, Z80230 80
reset timing, Z85230 89
resetting highest IUS from lower priority 101
SDLC frame status FIFO 29
SDLC loop 18
standard and open-drain test conditions 76
system timing, Z80230 86
system timing, Z85230 98
transmit data path 8
TxIP latching 27
PRELIMINARY
Index