Z8523L08VEG Datasheet, PDF (16/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
11
Table 2. ESCC Read Registers
Register Name
RR0
RR1
RR2A
RR2B
RR3A
RR4
RR5
RR6
RR7
RR8
RR9
RR10
RR11
RR12
RR13
RR14
RR15
Functions
Transmit, Receive, and External Status
Special Receive Condition Status Bits
Unmodified Interrupt Vector
Modified Interrupt Vector
Interrupt Pending Bits
WR4 Mirror, if WR7’ bit D6 equals 1
WR5 Mirror, if WR7’ bit D6 equals 1
SDLC Frame LSB Byte Count, if WR15 bit D2 equals 1
SDLC Frame 10 X 19 FIFO Status and MSB Byte Count, if
WR15 bit DS equals 1
Receive Data FIFO, 8 Bits Deep
WR9 Mirror, if WR7’ bit D6 Equals 1
Miscellaneous Status Bits
WR11 Mirror, if WR7’ bit D6 Equals 1
Lower Byte of BRG Time Constant
Upper Byte of BRG Time Constant
WR14 Mirror, if WR7’ bit D6 Equals 1
WR 15 Mirror, if WR7’ bit D6 Equals 1
There are three modes used to move data into and out of the ESCC:
1. POLLING
2. INTERRUPT (vectored and non-vectored)
3. BLOCK TRANSFER
The BLOCK TRANSFER mode can be implemented under CPU or DMA control.
POLLING
When POLLING, data interrupts are disabled, three registers in the ESCC are automati-
cally updated whenever any function is performed. For example, end-of-frame (EOF) in
SDLC mode sets a bit in one of these status registers. The purpose of POLLING is for the
CPU to periodically read a status register until the register contents indicate the need that
data requires transfer. RR0 is the only register that must be read to determine if data needs
to be transferred. An alternative to polling RR0 for each channel is to poll the Interrupt
PS005308-0609
Functional Description