Z8523L08VEG Datasheet, PDF (22/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
17
CRC checking for SYNCHRONOUS BYTE-ORIENTED mode is delayed by one charac-
ter time so that the CPU may disable CRC checking on specific characters. This action
permits the implementation of protocols such as IBM BISYNC.
Both CRC-16 (X¹⁶ + X¹⁵ + X² + 1) and CRC-CCITT (X¹⁶ + X¹² + X⁵ + 1) error checking
polynomials are supported. Either polynomial may be selected in all synchronous modes.
You can preset the CRC generator and checker to all 1s or all 0s. The ESCC also provides
a feature that automatically transmits CRC data when no other data is available for trans-
mission. This feature enables high-speed transmissions under DMA control, with no need
for CPU intervention at the end of a message. When there is no data or CRC to send in the
SYNCHRONOUS mode, the transmitter inserts 6-, 8-, 12-, or 16-bit SYNC characters,
regardless of the programmed character length.
SDLC Mode
The ESCC supports SYNCHRONOUS bit-oriented protocols, such as SDLC and 
High-Level Data Link Control (HDLC), by performing automatic flag sending, zero inser-
tion, and CRC generation.
A special command is used to abort a frame which is in transmission. At the end of a mes-
sage, the ESCC automatically transmits the CRC and trailing flag when the transmitter
underruns. The transmitter may also be programmed to send an idle line consisting of con-
tinuous flag characters or a steady marking condition.
If a transmit underrun occurs in the middle of a message, an External/Status interrupt
warns the CPU of this status change so that an Abort command can be issued. The ESCC
may also be programmed to send an Abort command by itself, in the event of an 
underrun, relieving the CPU of the task. The last character of a frame may consist of 1- to
8-bits, allowing reception of frames of any length.
The receiver automatically synchronizes on the leading flag of a frame in SDLC or HDLC
and provides a synchronization signal on the SYNC pin (an interrupt may also be pro-
grammed). The receiver may search for frames addressed by 1-byte or 4-bits within a byte
of a user-specified address or for a global broadcast address. Frames not matching either
the user-selected address or broadcast address are ignored.
The number of address bytes are extended under software control. To receive data, an
interrupt can be selected on the first received character, or on every character, or On Spe-
cial Condition Only (EOF). The receiver automatically deletes all zeros inserted by the
transmitter during character assembly. CRC is also calculated and is automatically
checked to validate frame transmission. At the end of transmission, the status of a received
frame is available in the status registers. In SDLC mode, the ESCC must be programmed
to use the CRC-CCITT polynomial, but the generator and checker may be pre-set to all 1s
or all 0s. The CRC data is inverted before transmission and the receiver checks against the
bit pattern 0001110100001111.
PS005308-0609
Functional Description