Z8523L08VEG Datasheet, PDF (41/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
36
Bits 2–0 of WR0 select registers 0–7. With the Point High command, Registers 8–15 are
selected. Table 7 lists details of the Z8530 Register Map.
Table 7. Z85230/L Register Map
A/B
PNT2
PNT1
PNT0
Write
85230
WR15 D2=0
0
0
0
0
WR0B
RR0B
0
0
0
0
WR1B
RR1B
0
0
0
1
WR2
RR2B
0
0
0
1
WR3B
RR3B
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
WR4B
WR5B
WR6B
WR7A
(RR0B)
(RR1B)
(RR2B)
(RR3B)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
WR0A
WR1A
WR2
WR3A
RR0A
RR1A
RR2A
RR3A
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
WR4A
WR5A
WR6A
WR7A
(RR0A)
(RR1A)
(RR2A)
(RR3A)
With Point High Command
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
WR8B
WR9
WR10B
WR11B
RR8B
(RR13B)
RR10B
(RR15B)
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
WR12B
WR13B
WR14B
WR15B
RR12B
RR13B
RR14B
RR15B
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
WR8A
WR9
WR10A
WR11A
RR8A
(RR13A)
RR10A
(RR15A)
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
WR12A
WR13A
WR14A
WR15A
RR12A
RR13A
RR14A
RR15A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
WR0B
WR1B
WR2
WR3B
RR0B
RR1B
RR2B
RR3B
Notes:
1. The register names in ( ) are the values read out from that register location.
2. WR15 bit D2 enables status FIFO function (not available on NMOS).
3. WR7’ bit D6 enables extend read function (only on ESCC).
85230
WR15 D2=1
RR0B
RR1B
RR2B
RR3B
(RR0B)
(RR1B)
RR6B
RR7B
RR0A
RR1A
RR2A
RR3A
(RR0A)
(RR1A)
RR6A
RR7A
RR8B
(RR13B)
RR10B
(RR15B)
RR12B
RR13B
RR14B
RR15B
RR8A
(RR13A)
RR10A
(RR15A)
RR12A
RR13A
RR14A
RR15A
RR0B
RR1B
RR2B
RR3B
85230
WR15 D2=1
WR7’ D6=1
RR0B
RR1B
RR2B
RR3B
(WR4B)
(WR5B)
RR6B
RR7B
RR0A
RR1A
RR2A
RR3A
(WR4A)
(WR5A)
RR6A
RR7A
RR8B
(WR3B)
RR10B
(WR10B)
RR12B
RR13B
(WR7’B)
RR15B
RR8A
(WR3A)
RR10A
(WR10A)
RR12A
RR13A
(WR7’A)
RR15A
RR0B
RR1B
RR2B
RR3B
PS005308-0609
Programming