Z8523L08VEG Datasheet, PDF (34/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
29
controller to transfer the next frame into memory while the CPU verifies the previously
received frame.
Frame Status FIFO Circuitry
SCC Status Register
RR1 Residue Bits (3)
Overrun, CRC Error
Byte Counter
Reset on Flag Detect
Increment on
Each Received Character
Enable Count in SDLC
5 Bits
FIFO Array
10- by 19- Bits
EOF Signal
14 Bits _{Status Read Complete}
Tail Pointer
4-Bit Counter
Head Pointer
4-Bit Counter
5 Bits
EOF=1 _{6 Bits} ^{8 Bits}
4-Bit Comparator
Over Equal
6-Bit MUX
EN
2 Bits
6 Bits
RR1
Bit Bit
76
Bits
5-0
RR6
FIFO
Enable
Interface
to SCC
See Notes:, next.
RR7 5 - 0 + RR6 7-0
14-Bit Byte Counter
(16 KB Maximum Count)
RR7 Bit 7
FIFO data-available status bit
(1 during read)
RR7 Bit 7
FIFO Overflow Status Bit
(1 on overflow)
WR15 Bit 2
Set Enables
Status FIFO
Figure 15. SDLC Frame Status FIFO
Notes:
1. All Sent bypasses MUX and equals contents of SCC Status Register.
2. Parity bits bypass MUX and equals contents of SCC Status Register.
3. EOF is set to 1 whenever reading from the FIFO.
Summarizing the operation: Data is received, assembled, and loaded into the 8-byte FIFO
before transferring to memory by the DMA controller.
PS005308-0609
Z80230/Z85230/L Enhancements