Z8523L08VEG Datasheet, PDF (18/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
13
+V_CC
Peripheral
IEI A7–A0INT INTACKIEO
Peripheral
IEI A7–A0 INTINTACKIEO
Peripheral
IEI A7–A0INTINTACK
+V_CC
A7–A0
INT
INTACK
Figure 7. ESCC Interrupt Priority Schedule
The ESCC can also execute an Interrupt Acknowledge cycle using software. Sometimes it
is difficult to create the INTACK signal with the necessary timing to acknowledge inter-
rupts and allow the nesting of interrupts. In such cases, interrupts can be acknowledged
with a software command to the ESCC. For more information, Z80230/Z85230/L
Enhancements on page 22
Interrupt Pending (IP) bits signal a need for interrupt servicing. When an IP bit is 1 and the
IEI input is High, the INT output is pulled Low, requesting an interrupt. In the ESCC, if an
IE bit is not set, then the IP for that source is never set. The IP bits are read in RR3A.
The Interrupt Under Service (IUS) bits signal that an interrupt request is serviced. If IUS is
set to 1, all interrupt sources of low priority in the ESCC and external to the ESCC are pre-
vented from requesting interrupts. The internal interrupt sources are inhibited by the state
of the internal daisy chain, while lower priority devices are inhibited by setting IEO Low
for subsequent peripherals. An IUS bit is set during an Interrupt Acknowledge cycle if
there are no higher priority devices requesting interrupt.
There are three type of interrupts as listed below:
1. Transmit
2. Receive
3. External/Status
Each interrupt type is enabled under program control with Channel A having higher prior-
ity than Channel B, and with Transmit, Receive, and External/Status interrupts prioritized
in that order within each channel. When the Transmit interrupt is enabled (WR1 bit 1 is 1),
the occurrence of the interrupt depends on the state of WR7’ bit 5. If WR7’ bit 5 is 0, the
CPU is interrupted when the top byte of the transmit First In First Out (FIFO) becomes
empty. If WR7’ bit 5 is 1, the CPU is interrupted when the transmit FIFO becomes com-
pletely empty. The transmit interrupt occurs when the data in the exit location of the
Transmit FIFO loads into the Transmit Shift Register and the Transmit FIFO becomes
completely empty. This condition means that there must be at least one character written
to the Tx FIFO for it to become empty.
PS005308-0609
Functional Description