Z8523L08VEG Datasheet, PDF (77/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
72
tor on A7-A0. WR9 bit 1 is set to 1 to disable the placing of a vector on a bus. The INT pin
also goes inactive in response to the falling edge of DS. There is only one DS per interrupt
acknowledge cycle.
IP bits in the Z80230 are updated by AS, which can delay interrupt requests if the proces-
sor does not supply AS strobes during the time in between accesses of the Z80230.
AS
CS0
A7–A0
Vector
DS
INTACK
IEI
IEO
INT
Figure 19. Z80230 Interrupt Acknowledge Cycle Timing
Z85230/L Timing
The ESCC generates internal control signals from WR and RD that relate to PCLK.
Because PCLK had no defined phase relationship with WR and RD, the circuitry generat-
ing the internal control signals provides time for metastable conditions to disappear. This
causes a recovery time related to PCLK. The recovery time applies only to bus transac-
tions involving the ESCC. The recovery time required for proper operation is specified
PS005308-0609
Z80230 Interface Timing