Z8523L08VEG Datasheet, PDF (24/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
19
SDLC Status FIFO
The ESCC’s ability to receive high speed back-to-back SDLC frames is maximized by a
10-bit deep by 19-bit wide status FIFO buffer. When enabled (through WR15 bit 2 is 1),
the storage area enables DMA to continue data transfer into the memory, so that the CPU
examines the message later. For each SDLC frame, 14 counter bits and 5 Status/Error bits
are stored. The byte count and status bits are accessed through Read Registers, RR6, and
RR7. RR6 and RR7 are only used when the SDLC FIFO buffer is enabled. The 10 x 19
status FIFO buffer is separate from the 8-byte receive data FIFO buffer.
Baud Rate Generator
Each channel in the ESCC contains a programmable BRG. Each generator consists of two
8-bit registers that form a 16-bit time constant, a 16-bit down counter, and a flip-flop on
the output, producing a square wave. At start-up, the flip-flop at the output is set High, the
value in the time constant register is loaded into the counter, and the count down begins.
When the BRG reaches zero, the output toggles, the counter is reloaded with the time con-
stant, and the process repeats. The time constant can be changed at any time, but the new
value does not take effect until the counter is loaded again.
The output of the BRG may be used as the Transmit clock, the Receive clock, or both. The
output can also drive the DPLL. For more information, see Digital Phase-Locked Loop.
If the receive clock or the transmit clock is not programmed to come from the TRxC pin,
the output of the BRG may be echoed out by the TRxC pin.
The following formula relates the time constant to the baud rate. PCLK or RTxC is the
clock input to the BRG. The clock mode is 1, 16, 32, or 64, as selected in WR 4 bits 6 and
7.
Time
Constant
=
PCLK or RTxC Frequency
2(Baud Rate) (Clock Mode)
-2
Digital Phase-Locked Loop
The ESCC contains a DPLL to recover clock information from a data stream with NRZI or
FM encoding. The DPLL is driven by a clock that is nominally 32 (NRZI) or 16 (FM)
times the data rate. The DPLL uses this clock, along with the data stream, to construct a
clock for the data. This clock is then used as the ESCC receive clock, the transmit clock,
or both. When the DPLL is selected as the transmit clock source, it provides a jitter-free
clock output. The clock output is the DPLL input frequency divided by the appropriate
divisor for the selected encoding technique.
For NRZI encoding, the DPLL counts the 32x clock to create nominal bit times. As the
32x clock is counted, the DPLL searches the incoming data stream for edges (either 1 to 0
or 0 to 1). When a transition is detected the DPLL makes a count adjustment (during the
next counting cycle), producing a terminal count closer to the center of the bit cell.
PS005308-0609
Functional Description