Z8523L08VEG Datasheet, PDF (28/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
23
By resetting WR7’ bit 3 to 0, applications which have a long latency to interrupts can gen-
erate the request to read data from the FIFO when one byte is available. The application
can then test the Receive Character Available bit to determine if more data is available.
By setting WR7’ bit 3 to 0, the ESCC can issue an interrupt when the receive FIFO is half
full (4 bytes available), allowing the frequency of interrupts to be reduced. If WR7’ bit 3 is
1, the Receive Character Available interrupt is generated when there are 4 bytes available.
If the ISR reads 4 bytes during each routine, the frequency of interrupts is reduced.
If WR7’ bit 3 is 1 and Receive Interrupt on All Characters and Special Conditions is
enabled, the receive character available interrupt is generated when four characters are
available. However, when a character is detected to have a special condition, an interrupt
is generated when the character is loaded into the top four bytes of the FIFO. Therefore,
the Special Condition ISR must be RR1 before reading the data to determine which byte
has the special condition.
Write Register 7 PRIME (WR7’)
A new register, WR7’, has been added to the ESCC to enable the programming of six new
features. The format of this register is listed in Table 4.
Table 4. Write Register 7 Prime (WR7’)
Bit
7
6
5
4
3
2
1
0
R/W
W
W
W
/W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Note: R = Read W = Write X = Indeterminate
Bit
Position
7
6
5
4
3
2
1
0
R/W
W
W
W
W
W
W
W
W
Value Description
0
Reserved, must be 0
Extended Read Enable
Transmit FIFO Int Level
DTR/REQ Timing Mode
Receive FIFO Int Level
Auto RTS Deactivation
Auto EOM Reset
Auto Transmit Flag
WR7’ is written by first setting Bit 0 of Write Register 15 (WR15 bit 0) to 1 and then
accessing WR7. All write commands to register 7 are to WR7’ while WR15 bit 0 is set to
PS005308-0609
Z80230/Z85230/L Enhancements