Z8523L08VEG Datasheet, PDF (14/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
9
CPU I/O
Internal Data Bus
I/O Data Buffer
Upper Byte (WR13)
Time Constant
Lower Byte (WR12)
Time Constant
Status FIFO
10 x 19 Frame
Rx Data FIFO
8 Bytes Deep
Rx Error FIFO
8 Bytes Deep
BRG
Input
16 Bit Down Counter Div 2
BRG
Output
DPLL IN
RxD
14 Bit Counter
Hunt Mode (BISYNC)
Rec. Error Logic
DPLL
DPLL
OUT
SYNC Register
and 0 Delete
3 Bits
SYNC
Receive Shift ^CRC
Register
Internal TXD
1 Bit
MUX
NRZI
Decode
MUX
CRC Delay
Register (8 Bits)
To Transmit Section
CRC Checker
SDLC-CRC
CRC Result
Figure 6. ESCC Receive Data Path
Input/Output Capabilities
System communication to and from the ESCC is accomplished using the 
ESCC register set. There are 17 Write registers and 16 Read registers. Many of the fea-
tures on the ESCC are enabled through a new register in the ESCC: Write Register 7
Prime (WR7’). This new register can be accessed if bit 0 or WR15 is set to 1. Table 1 on
page 10 lists the Write registers and a brief description of their functions. Table 2 on page
11 lists the Read Registers.
PS005308-0609
Functional Description