Z8523L08VEG Datasheet, PDF (104/118 Pages) Zilog, Inc. – Enhanced Serial Communications Controller

Z80230/Z85230/L
Product Specification
99
Z80230/Z85230/L Errata
The current revision of Zilog’s ESCC has six known bugs. This section identifies these
bugs and provides workarounds.
IUS Problem Description
The IUS problem occurs under the following conditions:
• SDLC 10x19 Status FIFO is enabled
• Interrupts on Receive Special Conditions only
This mode is intended for an application where received characters are read by a DMA
controller. EOF is treated differently from other special conditions (for example, parity
error, overrun error, and CRC error).
When EOF is detected, the following conditions occur:
• A Receive Character Available (RCA) interrupt is generated, rather than the Special
Conditions interrupt, as in other operating modes.
• The data FIFO is not locked, as in other operating modes, and is known as the Anti-
Lock feature.
This feature allows the processor to service the EOF interrupt with more latency. Immedi-
ate attention from the processor is not necessary because the data FIFO is not locked.
Incoming data can still be delivered to the Receive FIFO and not get lost. It also allows for
operation with no servicing of the interrupt.
When the EOF interrupt (RCA interrupt) is serviced, the processor must use the Reset
Highest IUS command to clear the EOF.
If an EOF interrupt occurs when another lower priority interrupt is enabled (for example,
Ext/Status interrupt is serviced) the Reset Highest IUS command issued by the lower
priority ISR (to clear out the pending interrupt) can accidentally clear the pending EOF
interrupt.
The Reset Highest IUS command clears the IP bit related to the EOF (in this mode, the
RCA IP bit) regardless of the priorities of the pending interrupts. This action causes errors
under the following circumstances:
• Another ESCC interrupt is being serviced (for example, an Ext/Status interrupt for
Transmitter Underrun in Full Duplex operation)
• The DMA reads a byte marked with EOF. The corresponding IP bit is set to 1 and the
INT line goes Low (highest priority interrupt in the daisy chain).
PS005308-0609
Z80230/Z85230/L Errata