Z87000 Datasheet, PDF (49/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Zilog
Z87000/Z87L00
Spread Spectrum Controllers
Table 37. Instruction Set Summary
Instruction Description Opcode
Synopsis
#
#
Operands
Words Cycles
Example
1
LD
Load destination
LD<dest>,<src>
with source
0000000
0000001
0001001
0000001
0000101
0000011
0000111
0000100
0001100
A,<hwregs>
A,<dregs>
A,<pregs>
A,<regind>
A,<memind>
A,<direct>
<direct>,A
<dregs>,<hwregs>
<pregs>,<simm>
1
1 LD A,X
1
1 LD A,D0:0
1
1 LD A,P0:1
1
1 LD A,@P1:1
1
3 LD A,@D0:0
1
1 LD A, 124
1
1 LD 124, A
1
1 LD DO:0, EXT7
1
1 LD P1:1,#%FA
0001010
0000110
0000010
0001001
0000001
0000100
0100101
0000101
0000001
<pregs>,<hwregs>
<regind>,<limm>
<regind>,<hwregs>
<hwregs>,<pregs>
<hwregs>,<dregs>
<hwregs>,<limm>
<hwregs>,<accind>
<hwregs>,<memind>
<hwregs>,<regind>
1
1 LD P1:1,EXT1
1
1 LD @P1:1,#%1234
1
1 LD @P1:1+,X
1
1 LD Y,P0:0
1
1 LD SR,D0:0
2
2 LD PC,#%1234
1
3 LD X,@A
1
3 LD Y,@D0:0
1
1 LD A,@P0:0-LOOP
0000000
<hwregs>,<hwregs>
1
1 LD X, EXT6
MLD
Multiply
1010010 MLD<srcl>,<srcl>
1010010 [,<bank switch>]
<hwregs>,<regind>
1
<hwregs>,<regind>,<ban 1
1 MLD A,@P0:0+LOOP
1 MLD A,@P1:0,OFF
1011011
1011011
k switch>
<regind>,<regind>
1
1 MLD @P1:1,@P2:0
1
1 MLD@P0:1,@P1:0,O
<regind>,<regind>,<bank
N
switch>
MPYA
Multiply and add
MPYA <srcl>,<src2>
1010010 [,<bank switch>]
<hwregs>,<regind>
1
1 MPYA A@P0:0
1010010
1011011
<hwregs>,<regind>,<ban 1
k switch>
1
1 MPYA A,@P1:0,OFF
1 MPYA @P1:1,@P2:0
1011011
<regind>,<regind>
1
<regind>,<regind>,<bank
switch>
1 MPYA@P0:1,@P1:0,
ON
MPYS
Multiply and
MPYS<src1>,<src2>
subtract
0010010 [,<bank switch>]
0010010
<hwregs>,<regind>
1
<hwregs>,<regind>,<ban 1
1 MPYS A,@P0:0
1 MPYS A,@P1:0,OFF
0011011
0011011
k switch>
1
<regind>,<regind>
1
<regind>,<regind>,<bank
switch>
1 MPYS @P1:1,@P2:0
1 MPYS@P0:1,@P1:0,
ON
NEG
Negate
NEG <cc>,A
1001000
<cc>, A
1
1 NEG NZ,A
1001000
A
1
1 NEG A
NOP
No operation
NOP
0000000
None
1
1 NOP
OR
Bitwise OR
OR <dest>,<src>
1101001
A, <pregs>
1
1 OR A, P0:1
1100001
1100100
A, <dregs>
A, <limm>
1
1 OR A, D0:1
2
2 OR A,#%202
1100101
1100011
1100001
1100000
A, <memind>
A, <direct>
A, <regind>
A, <hwregs>
1
3 OR A,@@P2:1+
1
1 OR A, %2C
1
1 OR A, @P1:0-LOOP
1
1 OR A, EXT6
DS96WRL0501
PRELIMINARY
1-49